M54451EVB.h 7.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF54451 EVB board.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M54451EVB_H
  12. #define _M54451EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_M54451EVB /* M54451EVB board */
  18. #define CONFIG_MCFUART
  19. #define CONFIG_SYS_UART_PORT (0)
  20. #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
  21. #undef CONFIG_WATCHDOG
  22. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  23. /*
  24. * BOOTP options
  25. */
  26. #define CONFIG_BOOTP_BOOTFILESIZE
  27. /* Network configuration */
  28. #define CONFIG_MCFFEC
  29. #ifdef CONFIG_MCFFEC
  30. # define CONFIG_MII_INIT 1
  31. # define CONFIG_SYS_DISCOVER_PHY
  32. # define CONFIG_SYS_RX_ETH_BUFFER 8
  33. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  34. # define CONFIG_SYS_FEC0_PINMUX 0
  35. # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  36. # define MCFFEC_TOUT_LOOP 50000
  37. # define CONFIG_ETHPRIME "FEC0"
  38. # define CONFIG_IPADDR 192.162.1.2
  39. # define CONFIG_NETMASK 255.255.255.0
  40. # define CONFIG_SERVERIP 192.162.1.1
  41. # define CONFIG_GATEWAYIP 192.162.1.1
  42. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  43. # ifndef CONFIG_SYS_DISCOVER_PHY
  44. # define FECDUPLEX FULL
  45. # define FECSPEED _100BASET
  46. # else
  47. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  48. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  49. # endif
  50. # endif /* CONFIG_SYS_DISCOVER_PHY */
  51. #endif
  52. #define CONFIG_HOSTNAME "M54451EVB"
  53. #ifdef CONFIG_SYS_STMICRO_BOOT
  54. /* ST Micro serial flash */
  55. #define CONFIG_SYS_LOAD_ADDR2 0x40010007
  56. #define CONFIG_EXTRA_ENV_SETTINGS \
  57. "netdev=eth0\0" \
  58. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  59. "loadaddr=0x40010000\0" \
  60. "sbfhdr=sbfhdr.bin\0" \
  61. "uboot=u-boot.bin\0" \
  62. "load=tftp ${loadaddr} ${sbfhdr};" \
  63. "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
  64. "upd=run load; run prog\0" \
  65. "prog=sf probe 0:1 1000000 3;" \
  66. "sf erase 0 30000;" \
  67. "sf write ${loadaddr} 0 30000;" \
  68. "save\0" \
  69. ""
  70. #else
  71. #define CONFIG_SYS_UBOOT_END 0x3FFFF
  72. #define CONFIG_EXTRA_ENV_SETTINGS \
  73. "netdev=eth0\0" \
  74. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  75. "loadaddr=40010000\0" \
  76. "u-boot=u-boot.bin\0" \
  77. "load=tftp ${loadaddr) ${u-boot}\0" \
  78. "upd=run load; run prog\0" \
  79. "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
  80. "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
  81. "cp.b ${loadaddr} 0 ${filesize};" \
  82. "save\0" \
  83. ""
  84. #endif
  85. /* Realtime clock */
  86. #define CONFIG_MCFRTC
  87. #undef RTC_DEBUG
  88. #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
  89. /* Timer */
  90. #define CONFIG_MCFTMR
  91. #undef CONFIG_MCFPIT
  92. /* I2c */
  93. #define CONFIG_SYS_I2C
  94. #define CONFIG_SYS_I2C_FSL
  95. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  96. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  97. #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
  98. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  99. /* DSPI and Serial Flash */
  100. #define CONFIG_CF_DSPI
  101. #define CONFIG_SERIAL_FLASH
  102. #define CONFIG_SYS_SBFHDR_SIZE 0x7
  103. /* Input, PCI, Flexbus, and VCO */
  104. #define CONFIG_EXTRA_CLOCK
  105. #define CONFIG_PRAM 2048 /* 2048 KB */
  106. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  107. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
  108. #define CONFIG_SYS_MBAR 0xFC000000
  109. /*
  110. * Low Level Configuration Settings
  111. * (address mappings, register initial values, etc.)
  112. * You should know what you are doing if you make changes here.
  113. */
  114. /*-----------------------------------------------------------------------
  115. * Definitions for initial stack pointer and data area (in DPRAM)
  116. */
  117. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  118. #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
  119. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  120. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
  121. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  122. #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
  123. /*-----------------------------------------------------------------------
  124. * Start addresses for the final memory configuration
  125. * (Set up by the startup code)
  126. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  127. */
  128. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  129. #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
  130. #define CONFIG_SYS_SDRAM_CFG1 0x33633F30
  131. #define CONFIG_SYS_SDRAM_CFG2 0x57670000
  132. #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
  133. #define CONFIG_SYS_SDRAM_EMOD 0x80810000
  134. #define CONFIG_SYS_SDRAM_MODE 0x008D0000
  135. #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
  136. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
  137. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  138. #ifdef CONFIG_CF_SBF
  139. # define CONFIG_SERIAL_BOOT
  140. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
  141. #else
  142. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  143. #endif
  144. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  145. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  146. /* Reserve 256 kB for malloc() */
  147. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  148. /*
  149. * For booting Linux, the board info and command line data
  150. * have to be in the first 8 MB of memory, since this is
  151. * the maximum mapped by the Linux kernel during initialization ??
  152. */
  153. /* Initial Memory map for Linux */
  154. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  155. /* Configuration for environment
  156. * Environment is not embedded in u-boot. First time runing may have env
  157. * crc error warning if there is no correct environment on the flash.
  158. */
  159. #undef CONFIG_ENV_OVERWRITE
  160. /* FLASH organization */
  161. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  162. #ifdef CONFIG_SYS_FLASH_CFI
  163. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  164. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  165. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  166. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  167. # define CONFIG_SYS_FLASH_CHECKSUM
  168. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
  169. #endif
  170. /*
  171. * This is setting for JFFS2 support in u-boot.
  172. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  173. */
  174. #ifdef CONFIG_CMD_JFFS2
  175. # define CONFIG_JFFS2_DEV "nor0"
  176. # define CONFIG_JFFS2_PART_SIZE 0x01000000
  177. # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
  178. #endif
  179. /* Cache Configuration */
  180. #define CONFIG_SYS_CACHELINE_SIZE 16
  181. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  182. CONFIG_SYS_INIT_RAM_SIZE - 8)
  183. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  184. CONFIG_SYS_INIT_RAM_SIZE - 4)
  185. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
  186. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  187. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  188. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  189. CF_ACR_EN | CF_ACR_SM_ALL)
  190. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
  191. CF_CACR_ICINVA | CF_CACR_EUSP)
  192. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  193. CF_CACR_DEC | CF_CACR_DDCM_P | \
  194. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  195. /*-----------------------------------------------------------------------
  196. * Memory bank definitions
  197. */
  198. /*
  199. * CS0 - NOR Flash 16MB
  200. * CS1 - Available
  201. * CS2 - Available
  202. * CS3 - Available
  203. * CS4 - Available
  204. * CS5 - Available
  205. */
  206. /* Flash */
  207. #define CONFIG_SYS_CS0_BASE 0x00000000
  208. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  209. #define CONFIG_SYS_CS0_CTRL 0x00004D80
  210. #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
  211. #endif /* _M54451EVB_H */