M54418TWR.h 8.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF54418 TWR board.
  4. *
  5. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M54418TWR_H
  12. #define _M54418TWR_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  20. #define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
  21. #undef CONFIG_WATCHDOG
  22. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  23. /*
  24. * BOOTP options
  25. */
  26. #define CONFIG_BOOTP_BOOTFILESIZE
  27. /*
  28. * NAND FLASH
  29. */
  30. #ifdef CONFIG_CMD_NAND
  31. #define CONFIG_JFFS2_NAND
  32. #define CONFIG_NAND_FSL_NFC
  33. #define CONFIG_SYS_NAND_BASE 0xFC0FC000
  34. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  35. #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  36. #define CONFIG_SYS_NAND_SELECT_DEVICE
  37. #endif
  38. /* Network configuration */
  39. #define CONFIG_MCFFEC
  40. #ifdef CONFIG_MCFFEC
  41. #define CONFIG_MII_INIT 1
  42. #define CONFIG_SYS_DISCOVER_PHY
  43. #define CONFIG_SYS_RX_ETH_BUFFER 2
  44. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  45. #define CONFIG_SYS_TX_ETH_BUFFER 2
  46. #define CONFIG_HAS_ETH1
  47. #define CONFIG_SYS_FEC0_PINMUX 0
  48. #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  49. #define CONFIG_SYS_FEC1_PINMUX 0
  50. #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
  51. #define MCFFEC_TOUT_LOOP 50000
  52. #define CONFIG_SYS_FEC0_PHYADDR 0
  53. #define CONFIG_SYS_FEC1_PHYADDR 1
  54. #define CONFIG_ETHPRIME "FEC0"
  55. #define CONFIG_IPADDR 192.168.1.2
  56. #define CONFIG_NETMASK 255.255.255.0
  57. #define CONFIG_SERVERIP 192.168.1.1
  58. #define CONFIG_GATEWAYIP 192.168.1.1
  59. #define CONFIG_SYS_FEC_BUF_USE_SRAM
  60. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  61. #ifndef CONFIG_SYS_DISCOVER_PHY
  62. #define FECDUPLEX FULL
  63. #define FECSPEED _100BASET
  64. #define LINKSTATUS 1
  65. #else
  66. #define LINKSTATUS 0
  67. #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  68. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  69. #endif
  70. #endif /* CONFIG_SYS_DISCOVER_PHY */
  71. #endif
  72. #define CONFIG_HOSTNAME "M54418TWR"
  73. #if defined(CONFIG_CF_SBF)
  74. /* ST Micro serial flash */
  75. #define CONFIG_SYS_LOAD_ADDR2 0x40010007
  76. #define CONFIG_EXTRA_ENV_SETTINGS \
  77. "netdev=eth0\0" \
  78. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  79. "loadaddr=0x40010000\0" \
  80. "sbfhdr=sbfhdr.bin\0" \
  81. "uboot=u-boot.bin\0" \
  82. "load=tftp ${loadaddr} ${sbfhdr};" \
  83. "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
  84. "upd=run load; run prog\0" \
  85. "prog=sf probe 0:1 1000000 3;" \
  86. "sf erase 0 40000;" \
  87. "sf write ${loadaddr} 0 40000;" \
  88. "save\0" \
  89. ""
  90. #elif defined(CONFIG_SYS_NAND_BOOT)
  91. #define CONFIG_EXTRA_ENV_SETTINGS \
  92. "netdev=eth0\0" \
  93. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  94. "loadaddr=0x40010000\0" \
  95. "u-boot=u-boot.bin\0" \
  96. "load=tftp ${loadaddr} ${u-boot};\0" \
  97. "upd=run load; run prog\0" \
  98. "prog=nand device 0;" \
  99. "nand erase 0 40000;" \
  100. "nb_update ${loadaddr} ${filesize};" \
  101. "save\0" \
  102. ""
  103. #else
  104. #define CONFIG_SYS_UBOOT_END 0x3FFFF
  105. #define CONFIG_EXTRA_ENV_SETTINGS \
  106. "netdev=eth0\0" \
  107. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  108. "loadaddr=40010000\0" \
  109. "u-boot=u-boot.bin\0" \
  110. "load=tftp ${loadaddr) ${u-boot}\0" \
  111. "upd=run load; run prog\0" \
  112. "prog=prot off mram" " ;" \
  113. "cp.b ${loadaddr} 0 ${filesize};" \
  114. "save\0" \
  115. ""
  116. #endif
  117. /* Realtime clock */
  118. #undef CONFIG_MCFRTC
  119. #define CONFIG_RTC_MCFRRTC
  120. #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
  121. /* Timer */
  122. #define CONFIG_MCFTMR
  123. #undef CONFIG_MCFPIT
  124. /* I2c */
  125. #undef CONFIG_SYS_FSL_I2C
  126. #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  127. /* I2C speed and slave address */
  128. #define CONFIG_SYS_I2C_SPEED 80000
  129. #define CONFIG_SYS_I2C_SLAVE 0x7F
  130. #define CONFIG_SYS_I2C_OFFSET 0x58000
  131. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  132. /* DSPI and Serial Flash */
  133. #define CONFIG_CF_DSPI
  134. #define CONFIG_SERIAL_FLASH
  135. #define CONFIG_SYS_SBFHDR_SIZE 0x7
  136. /* Input, PCI, Flexbus, and VCO */
  137. #define CONFIG_EXTRA_CLOCK
  138. #define CONFIG_PRAM 2048 /* 2048 KB */
  139. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
  140. #define CONFIG_SYS_MBAR 0xFC000000
  141. /*
  142. * Low Level Configuration Settings
  143. * (address mappings, register initial values, etc.)
  144. * You should know what you are doing if you make changes here.
  145. */
  146. /*-----------------------------------------------------------------------
  147. * Definitions for initial stack pointer and data area (in DPRAM)
  148. */
  149. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  150. /* End of used area in internal SRAM */
  151. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
  152. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  153. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
  154. GENERATED_GBL_DATA_SIZE) - 32)
  155. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  156. #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
  157. /*-----------------------------------------------------------------------
  158. * Start addresses for the final memory configuration
  159. * (Set up by the startup code)
  160. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  161. */
  162. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  163. #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
  164. #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
  165. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  166. #define CONFIG_SYS_DRAM_TEST
  167. #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
  168. #define CONFIG_SERIAL_BOOT
  169. #endif
  170. #if defined(CONFIG_SERIAL_BOOT)
  171. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
  172. #else
  173. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  174. #endif
  175. #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
  176. /* Reserve 256 kB for Monitor */
  177. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  178. /* Reserve 256 kB for malloc() */
  179. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  180. /*
  181. * For booting Linux, the board info and command line data
  182. * have to be in the first 8 MB of memory, since this is
  183. * the maximum mapped by the Linux kernel during initialization ??
  184. */
  185. /* Initial Memory map for Linux */
  186. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
  187. (CONFIG_SYS_SDRAM_SIZE << 20))
  188. /* Configuration for environment
  189. * Environment is embedded in u-boot in the second sector of the flash
  190. */
  191. #undef CONFIG_ENV_OVERWRITE
  192. /* FLASH organization */
  193. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  194. #ifdef CONFIG_SYS_FLASH_CFI
  195. /* Max size that the board might have */
  196. #define CONFIG_SYS_FLASH_SIZE 0x1000000
  197. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  198. /* max number of memory banks */
  199. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  200. /* max number of sectors on one chip */
  201. #define CONFIG_SYS_MAX_FLASH_SECT 270
  202. /* "Real" (hardware) sectors protection */
  203. #define CONFIG_SYS_FLASH_CHECKSUM
  204. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
  205. #else
  206. /* max number of sectors on one chip */
  207. #define CONFIG_SYS_MAX_FLASH_SECT 270
  208. /* max number of sectors on one chip */
  209. #define CONFIG_SYS_MAX_FLASH_BANKS 0
  210. #endif
  211. /*
  212. * This is setting for JFFS2 support in u-boot.
  213. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  214. */
  215. #ifdef CONFIG_CMD_JFFS2
  216. #define CONFIG_JFFS2_DEV "nand0"
  217. #define CONFIG_JFFS2_PART_OFFSET (0x800000)
  218. #endif
  219. /* Cache Configuration */
  220. #define CONFIG_SYS_CACHELINE_SIZE 16
  221. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  222. CONFIG_SYS_INIT_RAM_SIZE - 8)
  223. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  224. CONFIG_SYS_INIT_RAM_SIZE - 4)
  225. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
  226. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  227. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  228. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  229. CF_ACR_EN | CF_ACR_SM_ALL)
  230. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
  231. CF_CACR_ICINVA | CF_CACR_EUSP)
  232. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  233. CF_CACR_DEC | CF_CACR_DDCM_P | \
  234. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  235. #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  236. CONFIG_SYS_INIT_RAM_SIZE - 12)
  237. /*-----------------------------------------------------------------------
  238. * Memory bank definitions
  239. */
  240. /*
  241. * CS0 - NOR Flash 16MB
  242. * CS1 - Available
  243. * CS2 - Available
  244. * CS3 - Available
  245. * CS4 - Available
  246. * CS5 - Available
  247. */
  248. /* Flash */
  249. #define CONFIG_SYS_CS0_BASE 0x00000000
  250. #define CONFIG_SYS_CS0_MASK 0x000F0101
  251. #define CONFIG_SYS_CS0_CTRL 0x00001D60
  252. #endif /* _M54418TWR_H */