M5373EVB.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF5373 FireEngine board.
  4. *
  5. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M5373EVB_H
  12. #define _M5373EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
  21. #define CONFIG_SYS_UNIFY_CACHE
  22. #define CONFIG_MCFFEC
  23. #ifdef CONFIG_MCFFEC
  24. # define CONFIG_MII_INIT 1
  25. # define CONFIG_SYS_DISCOVER_PHY
  26. # define CONFIG_SYS_RX_ETH_BUFFER 8
  27. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  28. # define CONFIG_SYS_FEC0_PINMUX 0
  29. # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  30. # define MCFFEC_TOUT_LOOP 50000
  31. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  32. # ifndef CONFIG_SYS_DISCOVER_PHY
  33. # define FECDUPLEX FULL
  34. # define FECSPEED _100BASET
  35. # else
  36. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  37. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  38. # endif
  39. # endif /* CONFIG_SYS_DISCOVER_PHY */
  40. #endif
  41. #define CONFIG_MCFRTC
  42. #undef RTC_DEBUG
  43. /* Timer */
  44. #define CONFIG_MCFTMR
  45. #undef CONFIG_MCFPIT
  46. /* I2C */
  47. #define CONFIG_SYS_I2C
  48. #define CONFIG_SYS_I2C_FSL
  49. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  50. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  51. #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
  52. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  53. #define CONFIG_UDP_CHECKSUM
  54. #ifdef CONFIG_MCFFEC
  55. # define CONFIG_IPADDR 192.162.1.2
  56. # define CONFIG_NETMASK 255.255.255.0
  57. # define CONFIG_SERVERIP 192.162.1.1
  58. # define CONFIG_GATEWAYIP 192.162.1.1
  59. #endif /* FEC_ENET */
  60. #define CONFIG_HOSTNAME "M5373EVB"
  61. #define CONFIG_EXTRA_ENV_SETTINGS \
  62. "netdev=eth0\0" \
  63. "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  64. "u-boot=u-boot.bin\0" \
  65. "load=tftp ${loadaddr) ${u-boot}\0" \
  66. "upd=run load; run prog\0" \
  67. "prog=prot off 0 3ffff;" \
  68. "era 0 3ffff;" \
  69. "cp.b ${loadaddr} 0 ${filesize};" \
  70. "save\0" \
  71. ""
  72. #define CONFIG_PRAM 512 /* 512 KB */
  73. #define CONFIG_SYS_LOAD_ADDR 0x40010000
  74. #define CONFIG_SYS_CLK 80000000
  75. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
  76. #define CONFIG_SYS_MBAR 0xFC000000
  77. #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
  78. /*
  79. * Low Level Configuration Settings
  80. * (address mappings, register initial values, etc.)
  81. * You should know what you are doing if you make changes here.
  82. */
  83. /*-----------------------------------------------------------------------
  84. * Definitions for initial stack pointer and data area (in DPRAM)
  85. */
  86. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  87. #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
  88. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  89. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  90. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  91. /*-----------------------------------------------------------------------
  92. * Start addresses for the final memory configuration
  93. * (Set up by the startup code)
  94. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  95. */
  96. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  97. #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
  98. #define CONFIG_SYS_SDRAM_CFG1 0x53722730
  99. #define CONFIG_SYS_SDRAM_CFG2 0x56670000
  100. #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
  101. #define CONFIG_SYS_SDRAM_EMOD 0x40010000
  102. #define CONFIG_SYS_SDRAM_MODE 0x018D0000
  103. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
  104. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  105. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  106. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  107. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  108. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  109. /*
  110. * For booting Linux, the board info and command line data
  111. * have to be in the first 8 MB of memory, since this is
  112. * the maximum mapped by the Linux kernel during initialization ??
  113. */
  114. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  115. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  116. /*-----------------------------------------------------------------------
  117. * FLASH organization
  118. */
  119. #ifdef CONFIG_SYS_FLASH_CFI
  120. # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
  121. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  122. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  123. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  124. #endif
  125. #ifdef CONFIG_NANDFLASH_SIZE
  126. # define CONFIG_SYS_MAX_NAND_DEVICE 1
  127. # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
  128. # define CONFIG_SYS_NAND_SIZE 1
  129. # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  130. # define NAND_ALLOW_ERASE_ALL 1
  131. # define CONFIG_JFFS2_NAND 1
  132. # define CONFIG_JFFS2_DEV "nand0"
  133. # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
  134. # define CONFIG_JFFS2_PART_OFFSET 0x00000000
  135. #endif
  136. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  137. /* Configuration for environment
  138. * Environment is embedded in u-boot in the second sector of the flash
  139. */
  140. #define LDS_BOARD_TEXT \
  141. . = DEFINED(env_offset) ? env_offset : .; \
  142. env/embedded.o(.text*);
  143. /*-----------------------------------------------------------------------
  144. * Cache Configuration
  145. */
  146. #define CONFIG_SYS_CACHELINE_SIZE 16
  147. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  148. CONFIG_SYS_INIT_RAM_SIZE - 8)
  149. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  150. CONFIG_SYS_INIT_RAM_SIZE - 4)
  151. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
  152. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  153. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  154. CF_ACR_EN | CF_ACR_SM_ALL)
  155. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
  156. CF_CACR_DCM_P)
  157. /*-----------------------------------------------------------------------
  158. * Chipselect bank definitions
  159. */
  160. /*
  161. * CS0 - NOR Flash 1, 2, 4, or 8MB
  162. * CS1 - CompactFlash and registers
  163. * CS2 - NAND Flash 16, 32, or 64MB
  164. * CS3 - Available
  165. * CS4 - Available
  166. * CS5 - Available
  167. */
  168. #define CONFIG_SYS_CS0_BASE 0
  169. #define CONFIG_SYS_CS0_MASK 0x007f0001
  170. #define CONFIG_SYS_CS0_CTRL 0x00001fa0
  171. #define CONFIG_SYS_CS1_BASE 0x10000000
  172. #define CONFIG_SYS_CS1_MASK 0x001f0001
  173. #define CONFIG_SYS_CS1_CTRL 0x002A3780
  174. #ifdef CONFIG_NANDFLASH_SIZE
  175. #define CONFIG_SYS_CS2_BASE 0x20000000
  176. #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
  177. #define CONFIG_SYS_CS2_CTRL 0x00001f60
  178. #endif
  179. #endif /* _M5373EVB_H */