M5272C3.h 5.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Motorola MC5272C3 board.
  4. *
  5. * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
  6. */
  7. /*
  8. * board/config.h - configuration options, board specific
  9. */
  10. #ifndef _M5272C3_H
  11. #define _M5272C3_H
  12. /*
  13. * High Level Configuration Options
  14. * (easy to change)
  15. */
  16. #define CONFIG_MCFTMR
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
  21. #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  22. /* Configuration for environment
  23. * Environment is embedded in u-boot in the second sector of the flash
  24. */
  25. #define LDS_BOARD_TEXT \
  26. . = DEFINED(env_offset) ? env_offset : .; \
  27. env/embedded.o(.text);
  28. /*
  29. * BOOTP options
  30. */
  31. #define CONFIG_BOOTP_BOOTFILESIZE
  32. /*
  33. * Command line configuration.
  34. */
  35. #define CONFIG_MCFFEC
  36. #ifdef CONFIG_MCFFEC
  37. # define CONFIG_MII_INIT 1
  38. # define CONFIG_SYS_DISCOVER_PHY
  39. # define CONFIG_SYS_RX_ETH_BUFFER 8
  40. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  41. # define CONFIG_SYS_FEC0_PINMUX 0
  42. # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  43. # define MCFFEC_TOUT_LOOP 50000
  44. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  45. # ifndef CONFIG_SYS_DISCOVER_PHY
  46. # define FECDUPLEX FULL
  47. # define FECSPEED _100BASET
  48. # else
  49. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  50. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  51. # endif
  52. # endif /* CONFIG_SYS_DISCOVER_PHY */
  53. #endif
  54. #ifdef CONFIG_MCFFEC
  55. # define CONFIG_IPADDR 192.162.1.2
  56. # define CONFIG_NETMASK 255.255.255.0
  57. # define CONFIG_SERVERIP 192.162.1.1
  58. # define CONFIG_GATEWAYIP 192.162.1.1
  59. #endif /* CONFIG_MCFFEC */
  60. #define CONFIG_HOSTNAME "M5272C3"
  61. #define CONFIG_EXTRA_ENV_SETTINGS \
  62. "netdev=eth0\0" \
  63. "loadaddr=10000\0" \
  64. "u-boot=u-boot.bin\0" \
  65. "load=tftp ${loadaddr) ${u-boot}\0" \
  66. "upd=run load; run prog\0" \
  67. "prog=prot off ffe00000 ffe3ffff;" \
  68. "era ffe00000 ffe3ffff;" \
  69. "cp.b ${loadaddr} ffe00000 ${filesize};"\
  70. "save\0" \
  71. ""
  72. #define CONFIG_SYS_LOAD_ADDR 0x20000
  73. #define CONFIG_SYS_MEMTEST_START 0x400
  74. #define CONFIG_SYS_MEMTEST_END 0x380000
  75. #define CONFIG_SYS_CLK 66000000
  76. /*
  77. * Low Level Configuration Settings
  78. * (address mappings, register initial values, etc.)
  79. * You should know what you are doing if you make changes here.
  80. */
  81. #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
  82. #define CONFIG_SYS_SCR 0x0003
  83. #define CONFIG_SYS_SPR 0xffff
  84. /*-----------------------------------------------------------------------
  85. * Definitions for initial stack pointer and data area (in DPRAM)
  86. */
  87. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  88. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
  89. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  90. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  91. /*-----------------------------------------------------------------------
  92. * Start addresses for the final memory configuration
  93. * (Set up by the startup code)
  94. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  95. */
  96. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  97. #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
  98. #define CONFIG_SYS_FLASH_BASE 0xffe00000
  99. #ifdef CONFIG_MONITOR_IS_IN_RAM
  100. #define CONFIG_SYS_MONITOR_BASE 0x20000
  101. #else
  102. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  103. #endif
  104. #define CONFIG_SYS_MONITOR_LEN 0x20000
  105. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  106. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  107. /*
  108. * For booting Linux, the board info and command line data
  109. * have to be in the first 8 MB of memory, since this is
  110. * the maximum mapped by the Linux kernel during initialization ??
  111. */
  112. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  113. /*
  114. * FLASH organization
  115. */
  116. #ifdef CONFIG_SYS_FLASH_CFI
  117. # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
  118. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  119. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  120. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  121. #endif
  122. /*-----------------------------------------------------------------------
  123. * Cache Configuration
  124. */
  125. #define CONFIG_SYS_CACHELINE_SIZE 16
  126. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  127. CONFIG_SYS_INIT_RAM_SIZE - 8)
  128. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  129. CONFIG_SYS_INIT_RAM_SIZE - 4)
  130. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
  131. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  132. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  133. CF_ACR_EN | CF_ACR_SM_ALL)
  134. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
  135. CF_CACR_DISD | CF_CACR_INVI | \
  136. CF_CACR_CEIB | CF_CACR_DCM | \
  137. CF_CACR_EUSP)
  138. /*-----------------------------------------------------------------------
  139. * Memory bank definitions
  140. */
  141. #define CONFIG_SYS_BR0_PRELIM 0xFFE00201
  142. #define CONFIG_SYS_OR0_PRELIM 0xFFE00014
  143. #define CONFIG_SYS_BR1_PRELIM 0
  144. #define CONFIG_SYS_OR1_PRELIM 0
  145. #define CONFIG_SYS_BR2_PRELIM 0x30000001
  146. #define CONFIG_SYS_OR2_PRELIM 0xFFF80000
  147. #define CONFIG_SYS_BR3_PRELIM 0
  148. #define CONFIG_SYS_OR3_PRELIM 0
  149. #define CONFIG_SYS_BR4_PRELIM 0
  150. #define CONFIG_SYS_OR4_PRELIM 0
  151. #define CONFIG_SYS_BR5_PRELIM 0
  152. #define CONFIG_SYS_OR5_PRELIM 0
  153. #define CONFIG_SYS_BR6_PRELIM 0
  154. #define CONFIG_SYS_OR6_PRELIM 0
  155. #define CONFIG_SYS_BR7_PRELIM 0x00000701
  156. #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
  157. /*-----------------------------------------------------------------------
  158. * Port configuration
  159. */
  160. #define CONFIG_SYS_PACNT 0x00000000
  161. #define CONFIG_SYS_PADDR 0x0000
  162. #define CONFIG_SYS_PADAT 0x0000
  163. #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
  164. #define CONFIG_SYS_PBDDR 0x0000
  165. #define CONFIG_SYS_PBDAT 0x0000
  166. #define CONFIG_SYS_PDCNT 0x00000000
  167. #endif /* _M5272C3_H */