M5235EVB.h 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF5329 FireEngine board.
  4. *
  5. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M5235EVB_H
  12. #define _M5235EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  21. /*
  22. * BOOTP options
  23. */
  24. #define CONFIG_BOOTP_BOOTFILESIZE
  25. #define CONFIG_MCFFEC
  26. #ifdef CONFIG_MCFFEC
  27. # define CONFIG_MII_INIT 1
  28. # define CONFIG_SYS_DISCOVER_PHY
  29. # define CONFIG_SYS_RX_ETH_BUFFER 8
  30. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  31. # define CONFIG_SYS_FEC0_PINMUX 0
  32. # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  33. # define MCFFEC_TOUT_LOOP 50000
  34. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  35. # ifndef CONFIG_SYS_DISCOVER_PHY
  36. # define FECDUPLEX FULL
  37. # define FECSPEED _100BASET
  38. # else
  39. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  40. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  41. # endif
  42. # endif /* CONFIG_SYS_DISCOVER_PHY */
  43. #endif
  44. /* Timer */
  45. #define CONFIG_MCFTMR
  46. #undef CONFIG_MCFPIT
  47. /* I2C */
  48. #define CONFIG_SYS_I2C
  49. #define CONFIG_SYS_i2C_FSL
  50. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  51. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  52. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
  53. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  54. #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
  55. #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
  56. #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
  57. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  58. #define CONFIG_BOOTFILE "u-boot.bin"
  59. #ifdef CONFIG_MCFFEC
  60. # define CONFIG_IPADDR 192.162.1.2
  61. # define CONFIG_NETMASK 255.255.255.0
  62. # define CONFIG_SERVERIP 192.162.1.1
  63. # define CONFIG_GATEWAYIP 192.162.1.1
  64. #endif /* FEC_ENET */
  65. #define CONFIG_HOSTNAME "M5235EVB"
  66. #define CONFIG_EXTRA_ENV_SETTINGS \
  67. "netdev=eth0\0" \
  68. "loadaddr=10000\0" \
  69. "u-boot=u-boot.bin\0" \
  70. "load=tftp ${loadaddr) ${u-boot}\0" \
  71. "upd=run load; run prog\0" \
  72. "prog=prot off ffe00000 ffe3ffff;" \
  73. "era ffe00000 ffe3ffff;" \
  74. "cp.b ${loadaddr} ffe00000 ${filesize};"\
  75. "save\0" \
  76. ""
  77. #define CONFIG_PRAM 512 /* 512 KB */
  78. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
  79. #define CONFIG_SYS_CLK 75000000
  80. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
  81. #define CONFIG_SYS_MBAR 0x40000000
  82. /*
  83. * Low Level Configuration Settings
  84. * (address mappings, register initial values, etc.)
  85. * You should know what you are doing if you make changes here.
  86. */
  87. /*-----------------------------------------------------------------------
  88. * Definitions for initial stack pointer and data area (in DPRAM)
  89. */
  90. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  91. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
  92. #define CONFIG_SYS_INIT_RAM_CTRL 0x21
  93. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
  94. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  95. /*-----------------------------------------------------------------------
  96. * Start addresses for the final memory configuration
  97. * (Set up by the startup code)
  98. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  99. */
  100. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  101. #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
  102. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
  103. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  104. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  105. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  106. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  107. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  108. /*
  109. * For booting Linux, the board info and command line data
  110. * have to be in the first 8 MB of memory, since this is
  111. * the maximum mapped by the Linux kernel during initialization ??
  112. */
  113. /* Initial Memory map for Linux */
  114. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  115. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  116. /*-----------------------------------------------------------------------
  117. * FLASH organization
  118. */
  119. #ifdef CONFIG_SYS_FLASH_CFI
  120. # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
  121. #ifdef NORFLASH_PS32BIT
  122. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  123. #else
  124. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  125. #endif
  126. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  127. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  128. #endif
  129. #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  130. /* Configuration for environment
  131. * Environment is embedded in u-boot in the second sector of the flash
  132. */
  133. #define LDS_BOARD_TEXT \
  134. . = DEFINED(env_offset) ? env_offset : .; \
  135. env/embedded.o(.text);
  136. /*-----------------------------------------------------------------------
  137. * Cache Configuration
  138. */
  139. #define CONFIG_SYS_CACHELINE_SIZE 16
  140. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  141. CONFIG_SYS_INIT_RAM_SIZE - 8)
  142. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  143. CONFIG_SYS_INIT_RAM_SIZE - 4)
  144. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
  145. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  146. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  147. CF_ACR_EN | CF_ACR_SM_ALL)
  148. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
  149. CF_CACR_CEIB | CF_CACR_DCM | \
  150. CF_CACR_EUSP)
  151. /*-----------------------------------------------------------------------
  152. * Chipselect bank definitions
  153. */
  154. /*
  155. * CS0 - NOR Flash 1, 2, 4, or 8MB
  156. * CS1 - Available
  157. * CS2 - Available
  158. * CS3 - Available
  159. * CS4 - Available
  160. * CS5 - Available
  161. * CS6 - Available
  162. * CS7 - Available
  163. */
  164. #ifdef NORFLASH_PS32BIT
  165. # define CONFIG_SYS_CS0_BASE 0xFFC00000
  166. # define CONFIG_SYS_CS0_MASK 0x003f0001
  167. # define CONFIG_SYS_CS0_CTRL 0x00001D00
  168. #else
  169. # define CONFIG_SYS_CS0_BASE 0xFFE00000
  170. # define CONFIG_SYS_CS0_MASK 0x001f0001
  171. # define CONFIG_SYS_CS0_CTRL 0x00001D80
  172. #endif
  173. #endif /* _M5329EVB_H */