BSC9132QDS.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * BSC9132 QDS board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #ifdef CONFIG_SDCARD
  11. #define CONFIG_RAMBOOT_SDCARD
  12. #define CONFIG_SYS_RAMBOOT
  13. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  14. #endif
  15. #ifdef CONFIG_SPIFLASH
  16. #define CONFIG_RAMBOOT_SPIFLASH
  17. #define CONFIG_SYS_RAMBOOT
  18. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  19. #endif
  20. #ifdef CONFIG_NAND_SECBOOT
  21. #define CONFIG_RAMBOOT_NAND
  22. #define CONFIG_SYS_RAMBOOT
  23. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  24. #endif
  25. #ifdef CONFIG_MTD_RAW_NAND
  26. #define CONFIG_SPL_INIT_MINIMAL
  27. #define CONFIG_SPL_FLUSH_IMAGE
  28. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  29. #define CONFIG_SPL_MAX_SIZE 8192
  30. #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
  31. #define CONFIG_SPL_RELOC_STACK 0x00100000
  32. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
  33. #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  34. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  35. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
  36. #endif
  37. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  38. #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
  39. #endif
  40. #ifdef CONFIG_SPL_BUILD
  41. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  42. #else
  43. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  44. #endif
  45. /* High Level Configuration Options */
  46. #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
  47. #if defined(CONFIG_PCI)
  48. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  49. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  50. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  51. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  52. /*
  53. * PCI Windows
  54. * Memory space is mapped 1-1, but I/O space must start from 0.
  55. */
  56. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  57. #define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
  58. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
  59. #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
  60. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
  61. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  62. #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
  63. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  64. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  65. #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
  66. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  67. #endif
  68. #define CONFIG_ENV_OVERWRITE
  69. #if defined(CONFIG_SYS_CLK_100_DDR_100)
  70. #define CONFIG_SYS_CLK_FREQ 100000000
  71. #define CONFIG_DDR_CLK_FREQ 100000000
  72. #elif defined(CONFIG_SYS_CLK_100_DDR_133)
  73. #define CONFIG_SYS_CLK_FREQ 100000000
  74. #define CONFIG_DDR_CLK_FREQ 133000000
  75. #endif
  76. #define CONFIG_HWCONFIG
  77. /*
  78. * These can be toggled for performance analysis, otherwise use default.
  79. */
  80. #define CONFIG_L2_CACHE /* toggle L2 cache */
  81. #define CONFIG_BTB /* enable branch predition */
  82. #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
  83. #define CONFIG_SYS_MEMTEST_END 0x01ffffff
  84. /* DDR Setup */
  85. #define CONFIG_SYS_SPD_BUS_NUM 0
  86. #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
  87. #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
  88. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  89. #define CONFIG_SYS_SDRAM_SIZE (1024)
  90. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  91. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  92. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  93. /* DDR3 Controller Settings */
  94. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  95. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  96. #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
  97. #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
  98. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  99. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  100. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  101. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  102. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  103. #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
  104. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  105. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  106. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  107. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  108. #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
  109. #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
  110. #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
  111. #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
  112. #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
  113. #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
  114. #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
  115. #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
  116. #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
  117. #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
  118. #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
  119. #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
  120. #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
  121. #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
  122. #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
  123. #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
  124. #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
  125. #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
  126. #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
  127. #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
  128. #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
  129. #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
  130. #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
  131. #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
  132. #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
  133. #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
  134. /*FIXME: the following params are constant w.r.t diff freq
  135. combinations. this should be removed later
  136. */
  137. #if CONFIG_DDR_CLK_FREQ == 100000000
  138. #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
  139. #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
  140. #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
  141. #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
  142. #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
  143. #elif CONFIG_DDR_CLK_FREQ == 133000000
  144. #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
  145. #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
  146. #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
  147. #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
  148. #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
  149. #else
  150. #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
  151. #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
  152. #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
  153. #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
  154. #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
  155. #endif
  156. /* relocated CCSRBAR */
  157. #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
  158. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
  159. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  160. /* DSP CCSRBAR */
  161. #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
  162. #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
  163. /*
  164. * IFC Definitions
  165. */
  166. /* NOR Flash on IFC */
  167. #define CONFIG_SYS_FLASH_BASE 0x88000000
  168. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
  169. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  170. #define CONFIG_SYS_NOR_CSPR 0x88000101
  171. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  172. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
  173. /* NOR Flash Timing Params */
  174. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
  175. | FTIM0_NOR_TEADC(0x03) \
  176. | FTIM0_NOR_TAVDS(0x00) \
  177. | FTIM0_NOR_TEAHC(0x0f))
  178. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
  179. | FTIM1_NOR_TRAD_NOR(0x09) \
  180. | FTIM1_NOR_TSEQRAD_NOR(0x09))
  181. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
  182. | FTIM2_NOR_TCH(0x4) \
  183. | FTIM2_NOR_TWPH(0x7) \
  184. | FTIM2_NOR_TWP(0x1e))
  185. #define CONFIG_SYS_NOR_FTIM3 0x0
  186. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  187. #define CONFIG_SYS_FLASH_QUIET_TEST
  188. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  189. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  190. #undef CONFIG_SYS_FLASH_CHECKSUM
  191. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  192. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  193. /* CFI for NOR Flash */
  194. #define CONFIG_SYS_FLASH_EMPTY_INFO
  195. /* NAND Flash on IFC */
  196. #define CONFIG_SYS_NAND_BASE 0xff800000
  197. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  198. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  199. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  200. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  201. | CSPR_V)
  202. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  203. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  204. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  205. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  206. | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
  207. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  208. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  209. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  210. /* NAND Flash Timing Params */
  211. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
  212. | FTIM0_NAND_TWP(0x05) \
  213. | FTIM0_NAND_TWCHT(0x02) \
  214. | FTIM0_NAND_TWH(0x04))
  215. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
  216. | FTIM1_NAND_TWBE(0x1e) \
  217. | FTIM1_NAND_TRR(0x07) \
  218. | FTIM1_NAND_TRP(0x05))
  219. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
  220. | FTIM2_NAND_TREH(0x04) \
  221. | FTIM2_NAND_TWHRE(0x11))
  222. #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
  223. #define CONFIG_SYS_NAND_DDR_LAW 11
  224. /* NAND */
  225. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  226. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  227. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  228. #ifndef CONFIG_SPL_BUILD
  229. #define CONFIG_FSL_QIXIS
  230. #endif
  231. #ifdef CONFIG_FSL_QIXIS
  232. #define CONFIG_SYS_FPGA_BASE 0xffb00000
  233. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  234. #define QIXIS_BASE CONFIG_SYS_FPGA_BASE
  235. #define QIXIS_LBMAP_SWITCH 9
  236. #define QIXIS_LBMAP_MASK 0x07
  237. #define QIXIS_LBMAP_SHIFT 0
  238. #define QIXIS_LBMAP_DFLTBANK 0x00
  239. #define QIXIS_LBMAP_ALTBANK 0x04
  240. #define QIXIS_RST_CTL_RESET 0x83
  241. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  242. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  243. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  244. #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
  245. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
  246. | CSPR_PORT_SIZE_8 \
  247. | CSPR_MSEL_GPCM \
  248. | CSPR_V)
  249. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  250. #define CONFIG_SYS_CSOR2 0x0
  251. /* CPLD Timing parameters for IFC CS3 */
  252. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  253. FTIM0_GPCM_TEADC(0x0e) | \
  254. FTIM0_GPCM_TEAHC(0x0e))
  255. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  256. FTIM1_GPCM_TRAD(0x1f))
  257. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  258. FTIM2_GPCM_TCH(0x8) | \
  259. FTIM2_GPCM_TWP(0x1f))
  260. #define CONFIG_SYS_CS2_FTIM3 0x0
  261. #endif
  262. /* Set up IFC registers for boot location NOR/NAND */
  263. #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
  264. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  265. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  266. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  267. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  268. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  269. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  270. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  271. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  272. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  273. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  274. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  275. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  276. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  277. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  278. #else
  279. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  280. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  281. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  282. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  283. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  284. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  285. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  286. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  287. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  288. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  289. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  290. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  291. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  292. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  293. #endif
  294. #define CONFIG_SYS_INIT_RAM_LOCK
  295. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  296. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
  297. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  298. - GENERATED_GBL_DATA_SIZE)
  299. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  300. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  301. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
  302. /* Serial Port */
  303. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  304. #define CONFIG_SYS_NS16550_SERIAL
  305. #define CONFIG_SYS_NS16550_REG_SIZE 1
  306. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  307. #ifdef CONFIG_SPL_BUILD
  308. #define CONFIG_NS16550_MIN_FUNCTIONS
  309. #endif
  310. #define CONFIG_SYS_BAUDRATE_TABLE \
  311. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  312. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  313. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  314. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
  315. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
  316. #define CONFIG_SYS_I2C
  317. #define CONFIG_SYS_I2C_FSL
  318. #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
  319. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  320. #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
  321. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  322. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  323. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  324. /* I2C EEPROM */
  325. #define CONFIG_ID_EEPROM
  326. #ifdef CONFIG_ID_EEPROM
  327. #define CONFIG_SYS_I2C_EEPROM_NXID
  328. #endif
  329. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  330. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  331. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  332. /* enable read and write access to EEPROM */
  333. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  334. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  335. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  336. /* I2C FPGA */
  337. #define CONFIG_I2C_FPGA
  338. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  339. #define CONFIG_RTC_DS3231
  340. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  341. /*
  342. * SPI interface will not be available in case of NAND boot SPI CS0 will be
  343. * used for SLIC
  344. */
  345. /* eSPI - Enhanced SPI */
  346. #if defined(CONFIG_TSEC_ENET)
  347. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  348. #define CONFIG_TSEC1 1
  349. #define CONFIG_TSEC1_NAME "eTSEC1"
  350. #define CONFIG_TSEC2 1
  351. #define CONFIG_TSEC2_NAME "eTSEC2"
  352. #define TSEC1_PHY_ADDR 0
  353. #define TSEC2_PHY_ADDR 1
  354. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  355. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  356. #define TSEC1_PHYIDX 0
  357. #define TSEC2_PHYIDX 0
  358. #define CONFIG_ETHPRIME "eTSEC1"
  359. /* TBI PHY configuration for SGMII mode */
  360. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  361. TBICR_PHY_RESET \
  362. | TBICR_ANEG_ENABLE \
  363. | TBICR_FULL_DUPLEX \
  364. | TBICR_SPEED1_SET \
  365. )
  366. #endif /* CONFIG_TSEC_ENET */
  367. #ifdef CONFIG_MMC
  368. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  369. #endif
  370. #ifdef CONFIG_USB_EHCI_HCD
  371. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  372. #define CONFIG_USB_EHCI_FSL
  373. #define CONFIG_HAS_FSL_DR_USB
  374. #endif
  375. /*
  376. * Environment
  377. */
  378. #if defined(CONFIG_RAMBOOT_SDCARD)
  379. #define CONFIG_FSL_FIXED_MMC_LOCATION
  380. #define CONFIG_SYS_MMC_ENV_DEV 0
  381. #elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
  382. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  383. #endif
  384. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  385. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  386. /*
  387. * Miscellaneous configurable options
  388. */
  389. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  390. /*
  391. * For booting Linux, the board info and command line data
  392. * have to be in the first 64 MB of memory, since this is
  393. * the maximum mapped by the Linux kernel during initialization.
  394. */
  395. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  396. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  397. #if defined(CONFIG_CMD_KGDB)
  398. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  399. #endif
  400. /*
  401. * Dynamic MTD Partition support with mtdparts
  402. */
  403. /*
  404. * Environment Configuration
  405. */
  406. #if defined(CONFIG_TSEC_ENET)
  407. #define CONFIG_HAS_ETH0
  408. #define CONFIG_HAS_ETH1
  409. #endif
  410. #define CONFIG_HOSTNAME "BSC9132qds"
  411. #define CONFIG_ROOTPATH "/opt/nfsroot"
  412. #define CONFIG_BOOTFILE "uImage"
  413. #define CONFIG_UBOOTPATH "u-boot.bin"
  414. #ifdef CONFIG_SDCARD
  415. #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
  416. #else
  417. #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
  418. #endif
  419. #define CONFIG_EXTRA_ENV_SETTINGS \
  420. "netdev=eth0\0" \
  421. "uboot=" CONFIG_UBOOTPATH "\0" \
  422. "loadaddr=1000000\0" \
  423. "bootfile=uImage\0" \
  424. "consoledev=ttyS0\0" \
  425. "ramdiskaddr=2000000\0" \
  426. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  427. "fdtaddr=1e00000\0" \
  428. "fdtfile=bsc9132qds.dtb\0" \
  429. "bdev=sda1\0" \
  430. CONFIG_DEF_HWCONFIG\
  431. "othbootargs=mem=880M ramdisk_size=600000 " \
  432. "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
  433. "isolcpus=0\0" \
  434. "usbext2boot=setenv bootargs root=/dev/ram rw " \
  435. "console=$consoledev,$baudrate $othbootargs; " \
  436. "usb start;" \
  437. "ext2load usb 0:4 $loadaddr $bootfile;" \
  438. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  439. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  440. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  441. "debug_halt_off=mw ff7e0e30 0xf0000000;"
  442. #define CONFIG_NFSBOOTCOMMAND \
  443. "setenv bootargs root=/dev/nfs rw " \
  444. "nfsroot=$serverip:$rootpath " \
  445. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  446. "console=$consoledev,$baudrate $othbootargs;" \
  447. "tftp $loadaddr $bootfile;" \
  448. "tftp $fdtaddr $fdtfile;" \
  449. "bootm $loadaddr - $fdtaddr"
  450. #define CONFIG_HDBOOT \
  451. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  452. "console=$consoledev,$baudrate $othbootargs;" \
  453. "usb start;" \
  454. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  455. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  456. "bootm $loadaddr - $fdtaddr"
  457. #define CONFIG_RAMBOOTCOMMAND \
  458. "setenv bootargs root=/dev/ram rw " \
  459. "console=$consoledev,$baudrate $othbootargs; " \
  460. "tftp $ramdiskaddr $ramdiskfile;" \
  461. "tftp $loadaddr $bootfile;" \
  462. "tftp $fdtaddr $fdtfile;" \
  463. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  464. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  465. #include <asm/fsl_secure_boot.h>
  466. #endif /* __CONFIG_H */