BSC9131RDB.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * BSC9131 RDB board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #define CONFIG_NAND_FSL_IFC
  11. #ifdef CONFIG_SPIFLASH
  12. #define CONFIG_RAMBOOT_SPIFLASH
  13. #define CONFIG_SYS_RAMBOOT
  14. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  15. #endif
  16. #ifdef CONFIG_MTD_RAW_NAND
  17. #define CONFIG_SPL_INIT_MINIMAL
  18. #define CONFIG_SPL_FLUSH_IMAGE
  19. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  20. #define CONFIG_SPL_MAX_SIZE 8192
  21. #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
  22. #define CONFIG_SPL_RELOC_STACK 0x00100000
  23. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
  24. #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  25. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  26. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
  27. #endif
  28. #ifdef CONFIG_SPL_BUILD
  29. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  30. #else
  31. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  32. #endif
  33. /* High Level Configuration Options */
  34. #define CONFIG_ENV_OVERWRITE
  35. #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
  36. #if defined(CONFIG_SYS_CLK_100)
  37. #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
  38. #else
  39. #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
  40. #endif
  41. #define CONFIG_HWCONFIG
  42. /*
  43. * These can be toggled for performance analysis, otherwise use default.
  44. */
  45. #define CONFIG_L2_CACHE /* toggle L2 cache */
  46. #define CONFIG_BTB /* enable branch predition */
  47. #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
  48. #define CONFIG_SYS_MEMTEST_END 0x01ffffff
  49. /* DDR Setup */
  50. #undef CONFIG_SYS_DDR_RAW_TIMING
  51. #undef CONFIG_DDR_SPD
  52. #define CONFIG_SYS_SPD_BUS_NUM 0
  53. #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
  54. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  55. #ifndef __ASSEMBLY__
  56. extern unsigned long get_sdram_size(void);
  57. #endif
  58. #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
  59. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  60. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  61. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  62. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  63. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  64. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  65. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  66. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  67. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  68. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  69. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  70. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  71. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  72. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  73. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  74. #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  75. #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
  76. #define CONFIG_SYS_DDR_TIMING_4 0x00000001
  77. #define CONFIG_SYS_DDR_TIMING_5 0x02401400
  78. #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
  79. #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
  80. #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
  81. #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
  82. #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
  83. #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
  84. #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
  85. #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
  86. #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
  87. /*
  88. * Base addresses -- Note these are effective addresses where the
  89. * actual resources get mapped (not physical addresses)
  90. */
  91. /* relocated CCSRBAR */
  92. #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
  93. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
  94. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
  95. /* CONFIG_SYS_IMMR */
  96. /* DSP CCSRBAR */
  97. #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
  98. #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
  99. /*
  100. * Memory map
  101. *
  102. * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
  103. * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
  104. * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
  105. * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
  106. * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
  107. * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
  108. * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
  109. * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
  110. * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
  111. * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
  112. *
  113. */
  114. /*
  115. * IFC Definitions
  116. */
  117. /* NAND Flash on IFC */
  118. #define CONFIG_SYS_NAND_BASE 0xff800000
  119. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  120. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  121. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
  122. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  123. | CSPR_V)
  124. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  125. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  126. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  127. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  128. | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
  129. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  130. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  131. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  132. /* NAND Flash Timing Params */
  133. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
  134. | FTIM0_NAND_TWP(0x05) \
  135. | FTIM0_NAND_TWCHT(0x02) \
  136. | FTIM0_NAND_TWH(0x04))
  137. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
  138. | FTIM1_NAND_TWBE(0x1E) \
  139. | FTIM1_NAND_TRR(0x07) \
  140. | FTIM1_NAND_TRP(0x05))
  141. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
  142. | FTIM2_NAND_TREH(0x04) \
  143. | FTIM2_NAND_TWHRE(0x11))
  144. #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
  145. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  146. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  147. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  148. #define CONFIG_SYS_NAND_DDR_LAW 11
  149. /* Set up IFC registers for boot location NAND */
  150. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  151. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  152. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  153. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  154. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  155. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  156. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  157. #define CONFIG_SYS_INIT_RAM_LOCK
  158. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  159. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
  160. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  161. - GENERATED_GBL_DATA_SIZE)
  162. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  163. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  164. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
  165. /* Serial Port */
  166. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  167. #define CONFIG_SYS_NS16550_SERIAL
  168. #define CONFIG_SYS_NS16550_REG_SIZE 1
  169. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  170. #ifdef CONFIG_SPL_BUILD
  171. #define CONFIG_NS16550_MIN_FUNCTIONS
  172. #endif
  173. #define CONFIG_SYS_BAUDRATE_TABLE \
  174. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  175. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  176. #define CONFIG_SYS_I2C
  177. #define CONFIG_SYS_I2C_FSL
  178. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  179. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  180. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  181. /* I2C EEPROM */
  182. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  183. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  184. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  185. /* eSPI - Enhanced SPI */
  186. #if defined(CONFIG_TSEC_ENET)
  187. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  188. #define CONFIG_TSEC1 1
  189. #define CONFIG_TSEC1_NAME "eTSEC1"
  190. #define CONFIG_TSEC2 1
  191. #define CONFIG_TSEC2_NAME "eTSEC2"
  192. #define TSEC1_PHY_ADDR 0
  193. #define TSEC2_PHY_ADDR 3
  194. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  195. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  196. #define TSEC1_PHYIDX 0
  197. #define TSEC2_PHYIDX 0
  198. #define CONFIG_ETHPRIME "eTSEC1"
  199. #endif /* CONFIG_TSEC_ENET */
  200. /*
  201. * Environment
  202. */
  203. #if defined(CONFIG_RAMBOOT_SPIFLASH)
  204. #elif defined(CONFIG_MTD_RAW_NAND)
  205. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  206. #endif
  207. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  208. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  209. /*
  210. * Miscellaneous configurable options
  211. */
  212. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  213. #if defined(CONFIG_CMD_KGDB)
  214. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  215. #else
  216. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  217. #endif
  218. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  219. /*
  220. * For booting Linux, the board info and command line data
  221. * have to be in the first 64 MB of memory, since this is
  222. * the maximum mapped by the Linux kernel during initialization.
  223. */
  224. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  225. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  226. #if defined(CONFIG_CMD_KGDB)
  227. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  228. #endif
  229. #ifdef CONFIG_USB_EHCI_HCD
  230. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  231. #define CONFIG_USB_EHCI_FSL
  232. #define CONFIG_HAS_FSL_DR_USB
  233. #endif
  234. /*
  235. * Dynamic MTD Partition support with mtdparts
  236. */
  237. /*
  238. * Environment Configuration
  239. */
  240. #if defined(CONFIG_TSEC_ENET)
  241. #define CONFIG_HAS_ETH0
  242. #endif
  243. #define CONFIG_HOSTNAME "BSC9131rdb"
  244. #define CONFIG_ROOTPATH "/opt/nfsroot"
  245. #define CONFIG_BOOTFILE "uImage"
  246. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  247. #define CONFIG_EXTRA_ENV_SETTINGS \
  248. "netdev=eth0\0" \
  249. "uboot=" CONFIG_UBOOTPATH "\0" \
  250. "loadaddr=1000000\0" \
  251. "bootfile=uImage\0" \
  252. "consoledev=ttyS0\0" \
  253. "ramdiskaddr=2000000\0" \
  254. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  255. "fdtaddr=1e00000\0" \
  256. "fdtfile=bsc9131rdb.dtb\0" \
  257. "bdev=sda1\0" \
  258. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
  259. "bootm_size=0x37000000\0" \
  260. "othbootargs=ramdisk_size=600000 " \
  261. "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
  262. "usbext2boot=setenv bootargs root=/dev/ram rw " \
  263. "console=$consoledev,$baudrate $othbootargs; " \
  264. "usb start;" \
  265. "ext2load usb 0:4 $loadaddr $bootfile;" \
  266. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  267. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  268. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  269. #define CONFIG_RAMBOOTCOMMAND \
  270. "setenv bootargs root=/dev/ram rw " \
  271. "console=$consoledev,$baudrate $othbootargs; " \
  272. "tftp $ramdiskaddr $ramdiskfile;" \
  273. "tftp $loadaddr $bootfile;" \
  274. "tftp $fdtaddr $fdtfile;" \
  275. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  276. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  277. #endif /* __CONFIG_H */