B4860QDS.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. /*
  8. * B4860 QDS board configuration file
  9. */
  10. #ifdef CONFIG_RAMBOOT_PBL
  11. #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  12. #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  13. #ifndef CONFIG_MTD_RAW_NAND
  14. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  15. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  16. #else
  17. #define CONFIG_SPL_FLUSH_IMAGE
  18. #define CONFIG_SPL_PAD_TO 0x40000
  19. #define CONFIG_SPL_MAX_SIZE 0x28000
  20. #define RESET_VECTOR_OFFSET 0x27FFC
  21. #define BOOT_PAGE_OFFSET 0x27000
  22. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  23. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  24. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  25. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  26. #ifdef CONFIG_SPL_BUILD
  27. #define CONFIG_SPL_SKIP_RELOCATE
  28. #define CONFIG_SPL_COMMON_INIT_DDR
  29. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  30. #endif
  31. #endif
  32. #endif
  33. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  34. /* Set 1M boot space */
  35. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  36. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  37. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  38. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  39. #endif
  40. /* High Level Configuration Options */
  41. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  42. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  43. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  44. #endif
  45. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  46. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  47. #define CONFIG_PCIE1 /* PCIE controller 1 */
  48. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  49. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  50. #ifndef CONFIG_ARCH_B4420
  51. #define CONFIG_SYS_SRIO
  52. #define CONFIG_SRIO1 /* SRIO port 1 */
  53. #define CONFIG_SRIO2 /* SRIO port 2 */
  54. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  55. #endif
  56. /* I2C bus multiplexer */
  57. #define I2C_MUX_PCA_ADDR 0x77
  58. /* VSC Crossbar switches */
  59. #define CONFIG_VSC_CROSSBAR
  60. #define I2C_CH_DEFAULT 0x8
  61. #define I2C_CH_VSC3316 0xc
  62. #define I2C_CH_VSC3308 0xd
  63. #define VSC3316_TX_ADDRESS 0x70
  64. #define VSC3316_RX_ADDRESS 0x71
  65. #define VSC3308_TX_ADDRESS 0x02
  66. #define VSC3308_RX_ADDRESS 0x03
  67. /* IDT clock synthesizers */
  68. #define CONFIG_IDT8T49N222A
  69. #define I2C_CH_IDT 0x9
  70. #define IDT_SERDES1_ADDRESS 0x6E
  71. #define IDT_SERDES2_ADDRESS 0x6C
  72. /* Voltage monitor on channel 2*/
  73. #define I2C_MUX_CH_VOL_MONITOR 0xa
  74. #define I2C_VOL_MONITOR_ADDR 0x40
  75. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  76. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  77. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  78. #define CONFIG_ZM7300
  79. #define I2C_MUX_CH_DPM 0xa
  80. #define I2C_DPM_ADDR 0x28
  81. #define CONFIG_ENV_OVERWRITE
  82. #if defined(CONFIG_SPIFLASH)
  83. #elif defined(CONFIG_SDCARD)
  84. #define CONFIG_SYS_MMC_ENV_DEV 0
  85. #endif
  86. #ifndef __ASSEMBLY__
  87. unsigned long get_board_sys_clk(void);
  88. unsigned long get_board_ddr_clk(void);
  89. #endif
  90. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  91. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  92. /*
  93. * These can be toggled for performance analysis, otherwise use default.
  94. */
  95. #define CONFIG_SYS_CACHE_STASHING
  96. #define CONFIG_BTB /* toggle branch predition */
  97. #define CONFIG_DDR_ECC
  98. #ifdef CONFIG_DDR_ECC
  99. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  100. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  101. #endif
  102. #define CONFIG_ENABLE_36BIT_PHYS
  103. #ifdef CONFIG_PHYS_64BIT
  104. #define CONFIG_ADDR_MAP
  105. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  106. #endif
  107. #if 0
  108. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  109. #endif
  110. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  111. #define CONFIG_SYS_MEMTEST_END 0x00400000
  112. /*
  113. * Config the L3 Cache as L3 SRAM
  114. */
  115. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  116. #define CONFIG_SYS_L3_SIZE 256 << 10
  117. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  118. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  119. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  120. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  121. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  122. #ifdef CONFIG_PHYS_64BIT
  123. #define CONFIG_SYS_DCSRBAR 0xf0000000
  124. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  125. #endif
  126. /* EEPROM */
  127. #define CONFIG_ID_EEPROM
  128. #define CONFIG_SYS_I2C_EEPROM_NXID
  129. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  130. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  131. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  132. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  133. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  134. /*
  135. * DDR Setup
  136. */
  137. #define CONFIG_VERY_BIG_RAM
  138. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  139. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  140. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  141. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  142. #define CONFIG_DDR_SPD
  143. #define CONFIG_SYS_DDR_RAW_TIMING
  144. #define CONFIG_SYS_SPD_BUS_NUM 0
  145. #define SPD_EEPROM_ADDRESS1 0x51
  146. #define SPD_EEPROM_ADDRESS2 0x53
  147. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  148. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  149. /*
  150. * IFC Definitions
  151. */
  152. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  153. #ifdef CONFIG_PHYS_64BIT
  154. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  155. #else
  156. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  157. #endif
  158. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  159. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  160. + 0x8000000) | \
  161. CSPR_PORT_SIZE_16 | \
  162. CSPR_MSEL_NOR | \
  163. CSPR_V)
  164. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  165. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  166. CSPR_PORT_SIZE_16 | \
  167. CSPR_MSEL_NOR | \
  168. CSPR_V)
  169. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  170. /* NOR Flash Timing Params */
  171. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
  172. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
  173. FTIM0_NOR_TEADC(0x04) | \
  174. FTIM0_NOR_TEAHC(0x20))
  175. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  176. FTIM1_NOR_TRAD_NOR(0x1A) |\
  177. FTIM1_NOR_TSEQRAD_NOR(0x13))
  178. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
  179. FTIM2_NOR_TCH(0x0E) | \
  180. FTIM2_NOR_TWPH(0x0E) | \
  181. FTIM2_NOR_TWP(0x1c))
  182. #define CONFIG_SYS_NOR_FTIM3 0x0
  183. #define CONFIG_SYS_FLASH_QUIET_TEST
  184. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  185. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  186. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  187. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  188. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  189. #define CONFIG_SYS_FLASH_EMPTY_INFO
  190. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  191. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  192. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  193. #define CONFIG_FSL_QIXIS_V2
  194. #define QIXIS_BASE 0xffdf0000
  195. #ifdef CONFIG_PHYS_64BIT
  196. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  197. #else
  198. #define QIXIS_BASE_PHYS QIXIS_BASE
  199. #endif
  200. #define QIXIS_LBMAP_SWITCH 0x01
  201. #define QIXIS_LBMAP_MASK 0x0f
  202. #define QIXIS_LBMAP_SHIFT 0
  203. #define QIXIS_LBMAP_DFLTBANK 0x00
  204. #define QIXIS_LBMAP_ALTBANK 0x02
  205. #define QIXIS_RST_CTL_RESET 0x31
  206. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  207. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  208. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  209. #define CONFIG_SYS_CSPR3_EXT (0xf)
  210. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  211. | CSPR_PORT_SIZE_8 \
  212. | CSPR_MSEL_GPCM \
  213. | CSPR_V)
  214. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  215. #define CONFIG_SYS_CSOR3 0x0
  216. /* QIXIS Timing parameters for IFC CS3 */
  217. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  218. FTIM0_GPCM_TEADC(0x0e) | \
  219. FTIM0_GPCM_TEAHC(0x0e))
  220. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  221. FTIM1_GPCM_TRAD(0x1f))
  222. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  223. FTIM2_GPCM_TCH(0x8) | \
  224. FTIM2_GPCM_TWP(0x1f))
  225. #define CONFIG_SYS_CS3_FTIM3 0x0
  226. /* NAND Flash on IFC */
  227. #define CONFIG_NAND_FSL_IFC
  228. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  229. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  230. #define CONFIG_SYS_NAND_BASE 0xff800000
  231. #ifdef CONFIG_PHYS_64BIT
  232. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  233. #else
  234. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  235. #endif
  236. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  237. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  238. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  239. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  240. | CSPR_V)
  241. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  242. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  243. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  244. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  245. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  246. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  247. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  248. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  249. #define CONFIG_SYS_NAND_ONFI_DETECTION
  250. /* ONFI NAND Flash mode0 Timing Params */
  251. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  252. FTIM0_NAND_TWP(0x18) | \
  253. FTIM0_NAND_TWCHT(0x07) | \
  254. FTIM0_NAND_TWH(0x0a))
  255. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  256. FTIM1_NAND_TWBE(0x39) | \
  257. FTIM1_NAND_TRR(0x0e) | \
  258. FTIM1_NAND_TRP(0x18))
  259. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  260. FTIM2_NAND_TREH(0x0a) | \
  261. FTIM2_NAND_TWHRE(0x1e))
  262. #define CONFIG_SYS_NAND_FTIM3 0x0
  263. #define CONFIG_SYS_NAND_DDR_LAW 11
  264. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  265. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  266. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  267. #if defined(CONFIG_MTD_RAW_NAND)
  268. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  269. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  270. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  271. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  272. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  273. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  274. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  275. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  276. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  277. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
  278. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  279. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  280. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  281. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  282. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  283. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  284. #else
  285. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  286. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  287. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  288. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  289. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  290. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  291. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  292. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  293. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  294. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  295. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  296. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  297. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  298. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  299. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  300. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  301. #endif
  302. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  303. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  304. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  305. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  306. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  307. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  308. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  309. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  310. #ifdef CONFIG_SPL_BUILD
  311. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  312. #else
  313. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  314. #endif
  315. #if defined(CONFIG_RAMBOOT_PBL)
  316. #define CONFIG_SYS_RAMBOOT
  317. #endif
  318. #define CONFIG_HWCONFIG
  319. /* define to use L1 as initial stack */
  320. #define CONFIG_L1_INIT_RAM
  321. #define CONFIG_SYS_INIT_RAM_LOCK
  322. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  323. #ifdef CONFIG_PHYS_64BIT
  324. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  325. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  326. /* The assembler doesn't like typecast */
  327. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  328. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  329. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  330. #else
  331. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
  332. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  333. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  334. #endif
  335. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  336. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  337. GENERATED_GBL_DATA_SIZE)
  338. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  339. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  340. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  341. /* Serial Port - controlled on board with jumper J8
  342. * open - index 2
  343. * shorted - index 1
  344. */
  345. #define CONFIG_SYS_NS16550_SERIAL
  346. #define CONFIG_SYS_NS16550_REG_SIZE 1
  347. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  348. #define CONFIG_SYS_BAUDRATE_TABLE \
  349. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  350. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  351. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  352. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  353. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  354. /* I2C */
  355. #define CONFIG_SYS_I2C
  356. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  357. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
  358. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  359. #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
  360. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  361. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  362. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
  363. /*
  364. * RTC configuration
  365. */
  366. #define RTC
  367. #define CONFIG_RTC_DS3231 1
  368. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  369. /*
  370. * RapidIO
  371. */
  372. #ifdef CONFIG_SYS_SRIO
  373. #ifdef CONFIG_SRIO1
  374. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  375. #ifdef CONFIG_PHYS_64BIT
  376. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  377. #else
  378. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  379. #endif
  380. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  381. #endif
  382. #ifdef CONFIG_SRIO2
  383. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  384. #ifdef CONFIG_PHYS_64BIT
  385. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  386. #else
  387. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  388. #endif
  389. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  390. #endif
  391. #endif
  392. /*
  393. * for slave u-boot IMAGE instored in master memory space,
  394. * PHYS must be aligned based on the SIZE
  395. */
  396. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  397. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  398. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  399. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  400. /*
  401. * for slave UCODE and ENV instored in master memory space,
  402. * PHYS must be aligned based on the SIZE
  403. */
  404. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  405. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  406. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  407. /* slave core release by master*/
  408. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  409. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  410. /*
  411. * SRIO_PCIE_BOOT - SLAVE
  412. */
  413. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  414. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  415. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  416. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  417. #endif
  418. /*
  419. * eSPI - Enhanced SPI
  420. */
  421. /*
  422. * MAPLE
  423. */
  424. #ifdef CONFIG_PHYS_64BIT
  425. #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
  426. #else
  427. #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
  428. #endif
  429. /*
  430. * General PCI
  431. * Memory space is mapped 1-1, but I/O space must start from 0.
  432. */
  433. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  434. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  435. #ifdef CONFIG_PHYS_64BIT
  436. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  437. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  438. #else
  439. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  440. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  441. #endif
  442. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  443. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  444. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  445. #ifdef CONFIG_PHYS_64BIT
  446. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  447. #else
  448. #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
  449. #endif
  450. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  451. /* Qman/Bman */
  452. #ifndef CONFIG_NOBQFMAN
  453. #define CONFIG_SYS_BMAN_NUM_PORTALS 25
  454. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  455. #ifdef CONFIG_PHYS_64BIT
  456. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  457. #else
  458. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  459. #endif
  460. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  461. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  462. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  463. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  464. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  465. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  466. CONFIG_SYS_BMAN_CENA_SIZE)
  467. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  468. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  469. #define CONFIG_SYS_QMAN_NUM_PORTALS 25
  470. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  471. #ifdef CONFIG_PHYS_64BIT
  472. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  473. #else
  474. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  475. #endif
  476. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  477. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  478. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  479. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  480. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  481. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  482. CONFIG_SYS_QMAN_CENA_SIZE)
  483. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  484. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  485. #define CONFIG_SYS_DPAA_FMAN
  486. #define CONFIG_SYS_DPAA_RMAN
  487. /* Default address of microcode for the Linux Fman driver */
  488. #if defined(CONFIG_SPIFLASH)
  489. /*
  490. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  491. * env, so we got 0x110000.
  492. */
  493. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  494. #elif defined(CONFIG_SDCARD)
  495. /*
  496. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  497. * about 545KB (1089 blocks), Env is stored after the image, and the env size is
  498. * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
  499. */
  500. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
  501. #elif defined(CONFIG_MTD_RAW_NAND)
  502. #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
  503. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  504. /*
  505. * Slave has no ucode locally, it can fetch this from remote. When implementing
  506. * in two corenet boards, slave's ucode could be stored in master's memory
  507. * space, the address can be mapped from slave TLB->slave LAW->
  508. * slave SRIO or PCIE outbound window->master inbound window->
  509. * master LAW->the ucode address in master's memory space.
  510. */
  511. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  512. #else
  513. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  514. #endif
  515. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  516. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  517. #endif /* CONFIG_NOBQFMAN */
  518. #ifdef CONFIG_SYS_DPAA_FMAN
  519. #define CONFIG_PHYLIB_10G
  520. #define CONFIG_PHY_VITESSE
  521. #define CONFIG_PHY_TERANETICS
  522. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  523. #define SGMII_CARD_PORT2_PHY_ADDR 0x10
  524. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  525. #define SGMII_CARD_PORT4_PHY_ADDR 0x11
  526. #endif
  527. #ifdef CONFIG_PCI
  528. #define CONFIG_PCI_INDIRECT_BRIDGE
  529. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  530. #endif /* CONFIG_PCI */
  531. #ifdef CONFIG_FMAN_ENET
  532. #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
  533. #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
  534. /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
  535. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
  536. #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
  537. #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
  538. #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
  539. #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
  540. #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
  541. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  542. #endif
  543. #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
  544. /*
  545. * Environment
  546. */
  547. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  548. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  549. /*
  550. * USB
  551. */
  552. #define CONFIG_HAS_FSL_DR_USB
  553. #ifdef CONFIG_HAS_FSL_DR_USB
  554. #ifdef CONFIG_USB_EHCI_HCD
  555. #define CONFIG_USB_EHCI_FSL
  556. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  557. #endif
  558. #endif
  559. /*
  560. * Miscellaneous configurable options
  561. */
  562. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  563. /*
  564. * For booting Linux, the board info and command line data
  565. * have to be in the first 64 MB of memory, since this is
  566. * the maximum mapped by the Linux kernel during initialization.
  567. */
  568. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  569. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  570. #ifdef CONFIG_CMD_KGDB
  571. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  572. #endif
  573. /*
  574. * Environment Configuration
  575. */
  576. #define CONFIG_ROOTPATH "/opt/nfsroot"
  577. #define CONFIG_BOOTFILE "uImage"
  578. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  579. /* default location for tftp and bootm */
  580. #define CONFIG_LOADADDR 1000000
  581. #define __USB_PHY_TYPE ulpi
  582. #ifdef CONFIG_ARCH_B4860
  583. #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
  584. "bank_intlv=cs0_cs1;" \
  585. "en_cpc:cpc2;"
  586. #else
  587. #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
  588. #endif
  589. #define CONFIG_EXTRA_ENV_SETTINGS \
  590. HWCONFIG \
  591. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  592. "netdev=eth0\0" \
  593. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  594. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  595. "tftpflash=tftpboot $loadaddr $uboot && " \
  596. "protect off $ubootaddr +$filesize && " \
  597. "erase $ubootaddr +$filesize && " \
  598. "cp.b $loadaddr $ubootaddr $filesize && " \
  599. "protect on $ubootaddr +$filesize && " \
  600. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  601. "consoledev=ttyS0\0" \
  602. "ramdiskaddr=2000000\0" \
  603. "ramdiskfile=b4860qds/ramdisk.uboot\0" \
  604. "fdtaddr=1e00000\0" \
  605. "fdtfile=b4860qds/b4860qds.dtb\0" \
  606. "bdev=sda3\0"
  607. /* For emulation this causes u-boot to jump to the start of the proof point
  608. app code automatically */
  609. #define CONFIG_PROOF_POINTS \
  610. "setenv bootargs root=/dev/$bdev rw " \
  611. "console=$consoledev,$baudrate $othbootargs;" \
  612. "cpu 1 release 0x29000000 - - -;" \
  613. "cpu 2 release 0x29000000 - - -;" \
  614. "cpu 3 release 0x29000000 - - -;" \
  615. "cpu 4 release 0x29000000 - - -;" \
  616. "cpu 5 release 0x29000000 - - -;" \
  617. "cpu 6 release 0x29000000 - - -;" \
  618. "cpu 7 release 0x29000000 - - -;" \
  619. "go 0x29000000"
  620. #define CONFIG_HVBOOT \
  621. "setenv bootargs config-addr=0x60000000; " \
  622. "bootm 0x01000000 - 0x00f00000"
  623. #define CONFIG_ALU \
  624. "setenv bootargs root=/dev/$bdev rw " \
  625. "console=$consoledev,$baudrate $othbootargs;" \
  626. "cpu 1 release 0x01000000 - - -;" \
  627. "cpu 2 release 0x01000000 - - -;" \
  628. "cpu 3 release 0x01000000 - - -;" \
  629. "cpu 4 release 0x01000000 - - -;" \
  630. "cpu 5 release 0x01000000 - - -;" \
  631. "cpu 6 release 0x01000000 - - -;" \
  632. "cpu 7 release 0x01000000 - - -;" \
  633. "go 0x01000000"
  634. #define CONFIG_LINUX \
  635. "setenv bootargs root=/dev/ram rw " \
  636. "console=$consoledev,$baudrate $othbootargs;" \
  637. "setenv ramdiskaddr 0x02000000;" \
  638. "setenv fdtaddr 0x01e00000;" \
  639. "setenv loadaddr 0x1000000;" \
  640. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  641. #define CONFIG_HDBOOT \
  642. "setenv bootargs root=/dev/$bdev rw " \
  643. "console=$consoledev,$baudrate $othbootargs;" \
  644. "tftp $loadaddr $bootfile;" \
  645. "tftp $fdtaddr $fdtfile;" \
  646. "bootm $loadaddr - $fdtaddr"
  647. #define CONFIG_NFSBOOTCOMMAND \
  648. "setenv bootargs root=/dev/nfs rw " \
  649. "nfsroot=$serverip:$rootpath " \
  650. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  651. "console=$consoledev,$baudrate $othbootargs;" \
  652. "tftp $loadaddr $bootfile;" \
  653. "tftp $fdtaddr $fdtfile;" \
  654. "bootm $loadaddr - $fdtaddr"
  655. #define CONFIG_RAMBOOTCOMMAND \
  656. "setenv bootargs root=/dev/ram rw " \
  657. "console=$consoledev,$baudrate $othbootargs;" \
  658. "tftp $ramdiskaddr $ramdiskfile;" \
  659. "tftp $loadaddr $bootfile;" \
  660. "tftp $fdtaddr $fdtfile;" \
  661. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  662. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  663. #include <asm/fsl_secure_boot.h>
  664. #endif /* __CONFIG_H */