regs.h 17 KB

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  1. /* $Id$ */
  2. #ifndef _REGS_H
  3. #define _REGS_H
  4. /* Special Purpose Registers */
  5. #define SPR_CR -1
  6. #define SPR_MSR -2
  7. #define SPR_XER 1
  8. #define SPR_LR 8
  9. #define SPR_CTR 9
  10. #define SPR_DSISR 18
  11. #define SPR_DAR 19
  12. #define SPR_DEC 22
  13. #define SPR_SRR0 26
  14. #define SPR_SRR1 27
  15. #define SPR_EIE 80
  16. #define SPR_EID 81
  17. #define SPR_CMPA 144
  18. #define SPR_CMPB 145
  19. #define SPR_CMPC 146
  20. #define SPR_CMPD 147
  21. #define SPR_ICR 148
  22. #define SPR_DER 149
  23. #define SPR_COUNTA 150
  24. #define SPR_COUNTB 151
  25. #define SPR_CMPE 152
  26. #define SPR_CMPF 153
  27. #define SPR_CMPG 154
  28. #define SPR_CMPH 155
  29. #define SPR_LCTRL1 156
  30. #define SPR_LCTRL2 157
  31. #define SPR_ICTRL 158
  32. #define SPR_BAR 159
  33. #define SPR_USPRG0 256
  34. #define SPR_SPRG4_RO 260
  35. #define SPR_SPRG5_RO 261
  36. #define SPR_SPRG6_RO 262
  37. #define SPR_SPRG7_RO 263
  38. #define SPR_SPRG0 272
  39. #define SPR_SPRG1 273
  40. #define SPR_SPRG2 274
  41. #define SPR_SPRG3 275
  42. #define SPR_SPRG4 276
  43. #define SPR_SPRG5 277
  44. #define SPR_SPRG6 278
  45. #define SPR_SPRG7 279
  46. #define SPR_EAR 282 /* MPC603e core */
  47. #define SPR_TBL 284
  48. #define SPR_TBU 285
  49. #define SPR_PVR 287
  50. #define SPR_IC_CST 560
  51. #define SPR_IC_ADR 561
  52. #define SPR_IC_DAT 562
  53. #define SPR_DC_CST 568
  54. #define SPR_DC_ADR 569
  55. #define SPR_DC_DAT 570
  56. #define SPR_DPDR 630
  57. #define SPR_IMMR 638
  58. #define SPR_MI_CTR 784
  59. #define SPR_MI_AP 786
  60. #define SPR_MI_EPN 787
  61. #define SPR_MI_TWC 789
  62. #define SPR_MI_RPN 790
  63. #define SPR_MD_CTR 792
  64. #define SPR_M_CASID 793
  65. #define SPR_MD_AP 794
  66. #define SPR_MD_EPN 795
  67. #define SPR_M_TWB 796
  68. #define SPR_MD_TWC 797
  69. #define SPR_MD_RPN 798
  70. #define SPR_M_TW 799
  71. #define SPR_MI_DBCAM 816
  72. #define SPR_MI_DBRAM0 817
  73. #define SPR_MI_DBRAM1 818
  74. #define SPR_MD_DBCAM 824
  75. #define SPR_MD_DBRAM0 825
  76. #define SPR_MD_DBRAM1 826
  77. #define SPR_ZPR 944
  78. #define SPR_PID 945
  79. #define SPR_CCR0 947
  80. #define SPR_IAC3 948
  81. #define SPR_IAC4 949
  82. #define SPR_DVC1 950
  83. #define SPR_DVC2 951
  84. #define SPR_SGR 953
  85. #define SPR_DCWR 954
  86. #define SPR_SLER 955
  87. #define SPR_SU0R 956
  88. #define SPR_DBCR1 957
  89. #define SPR_ICDBDR 979
  90. #define SPR_ESR 980
  91. #define SPR_DEAR 981
  92. #define SPR_EVPR 982
  93. #define SPR_TSR 984
  94. #define SPR_TCR 986
  95. #define SPR_PIT 987
  96. #define SPR_SRR2 990
  97. #define SPR_SRR3 991
  98. #define SPR_DBSR 1008
  99. #define SPR_DBCR0 1010
  100. #define SPR_IABR 1010 /* MPC603e core */
  101. #define SPR_IAC1 1012
  102. #define SPR_IAC2 1013
  103. #define SPR_DAC1 1014
  104. #define SPR_DAC2 1015
  105. #define SPR_DCCR 1018
  106. #define SPR_ICCR 1019
  107. /* Bits for the DBCR0 register */
  108. #define DBCR0_EDM 0x80000000
  109. #define DBCR0_IDM 0x40000000
  110. #define DBCR0_RST 0x30000000
  111. #define DBCR0_IC 0x08000000
  112. #define DBCR0_BT 0x04000000
  113. #define DBCR0_EDE 0x02000000
  114. #define DBCR0_TDE 0x01000000
  115. #define DBCR0_IA1 0x00800000
  116. #define DBCR0_IA2 0x00400000
  117. #define DBCR0_IA12 0x00200000
  118. #define DBCR0_IA12X 0x00100000
  119. #define DBCR0_IA3 0x00080000
  120. #define DBCR0_IA4 0x00040000
  121. #define DBCR0_IA34 0x00020000
  122. #define DBCR0_IA34X 0x00010000
  123. #define DBCR0_IA12T 0x00008000
  124. #define DBCR0_IA34T 0x00004000
  125. #define DBCR0_FT 0x00000001
  126. /* Bits for the DBCR1 register */
  127. #define DBCR1_D1R 0x80000000
  128. #define DBCR1_D2R 0x40000000
  129. #define DBCR1_D1W 0x20000000
  130. #define DBCR1_D2W 0x10000000
  131. #define DBCR1_D1S 0x0C000000
  132. #define DBCR1_D2S 0x03000000
  133. #define DBCR1_DA12 0x00800000
  134. #define DBCR1_DA12X 0x00400000
  135. #define DBCR1_DV1M 0x000C0000
  136. #define DBCR1_DV2M 0x00030000
  137. #define DBCR1_DV1BE 0x0000F000
  138. #define DBCR1_DV2BE 0x00000F00
  139. /*
  140. * DBSR bits which have conflicting definitions on true Book E versus PPC40x
  141. */
  142. #ifdef CONFIG_BOOKE
  143. #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */
  144. #define DBSR_IA2 0x00400000 /* Instr Address Compare 2 Event */
  145. #define DBSR_IA3 0x00200000 /* Instr Address Compare 3 Event */
  146. #define DBSR_IA4 0x00100000 /* Instr Address Compare 4 Event */
  147. #endif
  148. #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */
  149. #define DBSR_IA2 0x02000000 /* Instr Address Compare 2 Event */
  150. #define DBSR_IA3 0x00080000 /* Instr Address Compare 3 Event */
  151. #define DBSR_IA4 0x00040000 /* Instr Address Compare 4 Event */
  152. struct spr_info {
  153. int spr_val;
  154. char spr_name[ 10 ];
  155. };
  156. extern struct spr_info spr_map[];
  157. extern const unsigned int n_sprs;
  158. #define SET_REGISTER( str, val ) \
  159. ({ unsigned long __value = (val); \
  160. asm volatile( str : : "r" (__value)); \
  161. __value; })
  162. #define GET_REGISTER( str ) \
  163. ({ unsigned long __value; \
  164. asm volatile( str : "=r" (__value) : ); \
  165. __value; })
  166. #define GET_CR() GET_REGISTER( "mfcr %0" )
  167. #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
  168. #define GET_MSR() GET_REGISTER( "mfmsr %0" )
  169. #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
  170. #define GET_XER() GET_REGISTER( "mfspr %0,1" )
  171. #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
  172. #define GET_LR() GET_REGISTER( "mfspr %0,8" )
  173. #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
  174. #define GET_CTR() GET_REGISTER( "mfspr %0,9" )
  175. #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
  176. #define GET_DSISR() GET_REGISTER( "mfspr %0,18" )
  177. #define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val )
  178. #define GET_DAR() GET_REGISTER( "mfspr %0,19" )
  179. #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
  180. #define GET_DEC() GET_REGISTER( "mfspr %0,22" )
  181. #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
  182. #define GET_SRR0() GET_REGISTER( "mfspr %0,26" )
  183. #define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val )
  184. #define GET_SRR1() GET_REGISTER( "mfspr %0,27" )
  185. #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
  186. #define GET_EIE() GET_REGISTER( "mfspr %0,80" )
  187. #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
  188. #define GET_EID() GET_REGISTER( "mfspr %0,81" )
  189. #define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val )
  190. #define GET_CMPA() GET_REGISTER( "mfspr %0,144" )
  191. #define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val )
  192. #define GET_CMPB() GET_REGISTER( "mfspr %0,145" )
  193. #define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val )
  194. #define GET_CMPC() GET_REGISTER( "mfspr %0,146" )
  195. #define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val )
  196. #define GET_CMPD() GET_REGISTER( "mfspr %0,147" )
  197. #define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val )
  198. #define GET_ICR() GET_REGISTER( "mfspr %0,148" )
  199. #define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val )
  200. #define GET_DER() GET_REGISTER( "mfspr %0,149" )
  201. #define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val )
  202. #define GET_COUNTA() GET_REGISTER( "mfspr %0,150" )
  203. #define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val )
  204. #define GET_COUNTB() GET_REGISTER( "mfspr %0,151" )
  205. #define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val )
  206. #define GET_CMPE() GET_REGISTER( "mfspr %0,152" )
  207. #define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val )
  208. #define GET_CMPF() GET_REGISTER( "mfspr %0,153" )
  209. #define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val )
  210. #define GET_CMPG() GET_REGISTER( "mfspr %0,154" )
  211. #define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val )
  212. #define GET_CMPH() GET_REGISTER( "mfspr %0,155" )
  213. #define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val )
  214. #define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" )
  215. #define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val )
  216. #define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" )
  217. #define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val )
  218. #define GET_ICTRL() GET_REGISTER( "mfspr %0,158" )
  219. #define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val )
  220. #define GET_BAR() GET_REGISTER( "mfspr %0,159" )
  221. #define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val )
  222. #define GET_USPRG0() GET_REGISTER( "mfspr %0,256" )
  223. #define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val )
  224. #define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" )
  225. #define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val )
  226. #define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" )
  227. #define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val )
  228. #define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" )
  229. #define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val )
  230. #define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" )
  231. #define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val )
  232. #define GET_SPRG0() GET_REGISTER( "mfspr %0,272" )
  233. #define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val )
  234. #define GET_SPRG1() GET_REGISTER( "mfspr %0,273" )
  235. #define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val )
  236. #define GET_SPRG2() GET_REGISTER( "mfspr %0,274" )
  237. #define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val )
  238. #define GET_SPRG3() GET_REGISTER( "mfspr %0,275" )
  239. #define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val )
  240. #define GET_SPRG4() GET_REGISTER( "mfspr %0,276" )
  241. #define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val )
  242. #define GET_SPRG5() GET_REGISTER( "mfspr %0,277" )
  243. #define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val )
  244. #define GET_SPRG6() GET_REGISTER( "mfspr %0,278" )
  245. #define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val )
  246. #define GET_SPRG7() GET_REGISTER( "mfspr %0,279" )
  247. #define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val )
  248. #define GET_EAR() GET_REGISTER( "mfspr %0,282" )
  249. #define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val )
  250. #define GET_TBL() GET_REGISTER( "mfspr %0,284" )
  251. #define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val )
  252. #define GET_TBU() GET_REGISTER( "mfspr %0,285" )
  253. #define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val )
  254. #define GET_PVR() GET_REGISTER( "mfspr %0,287" )
  255. #define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val )
  256. #define GET_IC_CST() GET_REGISTER( "mfspr %0,560" )
  257. #define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val )
  258. #define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" )
  259. #define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val )
  260. #define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" )
  261. #define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val )
  262. #define GET_DC_CST() GET_REGISTER( "mfspr %0,568" )
  263. #define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val )
  264. #define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" )
  265. #define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val )
  266. #define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" )
  267. #define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val )
  268. #define GET_DPDR() GET_REGISTER( "mfspr %0,630" )
  269. #define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val )
  270. #define GET_IMMR() GET_REGISTER( "mfspr %0,638" )
  271. #define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val )
  272. #define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" )
  273. #define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val )
  274. #define GET_MI_AP() GET_REGISTER( "mfspr %0,786" )
  275. #define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val )
  276. #define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" )
  277. #define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val )
  278. #define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" )
  279. #define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val )
  280. #define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" )
  281. #define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val )
  282. #define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" )
  283. #define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val )
  284. #define GET_M_CASID() GET_REGISTER( "mfspr %0,793" )
  285. #define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val )
  286. #define GET_MD_AP() GET_REGISTER( "mfspr %0,794" )
  287. #define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val )
  288. #define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" )
  289. #define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val )
  290. #define GET_M_TWB() GET_REGISTER( "mfspr %0,796" )
  291. #define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val )
  292. #define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" )
  293. #define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val )
  294. #define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" )
  295. #define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val )
  296. #define GET_M_TW() GET_REGISTER( "mfspr %0,799" )
  297. #define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val )
  298. #define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" )
  299. #define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val )
  300. #define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" )
  301. #define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val )
  302. #define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" )
  303. #define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val )
  304. #define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" )
  305. #define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val )
  306. #define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" )
  307. #define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val )
  308. #define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" )
  309. #define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val )
  310. #define GET_ZPR() GET_REGISTER( "mfspr %0,944" )
  311. #define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val )
  312. #define GET_PID() GET_REGISTER( "mfspr %0,945" )
  313. #define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val )
  314. #define GET_CCR0() GET_REGISTER( "mfspr %0,947" )
  315. #define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val )
  316. #define GET_IAC3() GET_REGISTER( "mfspr %0,948" )
  317. #define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val )
  318. #define GET_IAC4() GET_REGISTER( "mfspr %0,949" )
  319. #define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val )
  320. #define GET_DVC1() GET_REGISTER( "mfspr %0,950" )
  321. #define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val )
  322. #define GET_DVC2() GET_REGISTER( "mfspr %0,951" )
  323. #define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val )
  324. #define GET_SGR() GET_REGISTER( "mfspr %0,953" )
  325. #define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val )
  326. #define GET_DCWR() GET_REGISTER( "mfspr %0,954" )
  327. #define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val )
  328. #define GET_SLER() GET_REGISTER( "mfspr %0,955" )
  329. #define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val )
  330. #define GET_SU0R() GET_REGISTER( "mfspr %0,956" )
  331. #define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val )
  332. #define GET_DBCR1() GET_REGISTER( "mfspr %0,957" )
  333. #define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val )
  334. #define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" )
  335. #define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val )
  336. #define GET_ESR() GET_REGISTER( "mfspr %0,980" )
  337. #define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val )
  338. #define GET_DEAR() GET_REGISTER( "mfspr %0,981" )
  339. #define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val )
  340. #define GET_EVPR() GET_REGISTER( "mfspr %0,982" )
  341. #define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val )
  342. #define GET_TSR() GET_REGISTER( "mfspr %0,984" )
  343. #define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val )
  344. #define GET_TCR() GET_REGISTER( "mfspr %0,986" )
  345. #define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val )
  346. #define GET_PIT() GET_REGISTER( "mfspr %0,987" )
  347. #define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val )
  348. #define GET_SRR2() GET_REGISTER( "mfspr %0,990" )
  349. #define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val )
  350. #define GET_SRR3() GET_REGISTER( "mfspr %0,991" )
  351. #define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val )
  352. #define GET_DBSR() GET_REGISTER( "mfspr %0,1008" )
  353. #define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val )
  354. #define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" )
  355. #define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val )
  356. #define GET_IABR() GET_REGISTER( "mfspr %0,1010" )
  357. #define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val )
  358. #define GET_IAC1() GET_REGISTER( "mfspr %0,1012" )
  359. #define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val )
  360. #define GET_IAC2() GET_REGISTER( "mfspr %0,1013" )
  361. #define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val )
  362. #define GET_DAC1() GET_REGISTER( "mfspr %0,1014" )
  363. #define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val )
  364. #define GET_DAC2() GET_REGISTER( "mfspr %0,1015" )
  365. #define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val )
  366. #define GET_DCCR() GET_REGISTER( "mfspr %0,1018" )
  367. #define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val )
  368. #define GET_ICCR() GET_REGISTER( "mfspr %0,1019" )
  369. #define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val )
  370. #endif /* _REGS_H */
  371. /*
  372. * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
  373. * All rights reserved.
  374. *
  375. * Redistribution and use in source and binary forms are freely
  376. * permitted provided that the above copyright notice and this
  377. * paragraph and the following disclaimer are duplicated in all
  378. * such forms.
  379. *
  380. * This software is provided "AS IS" and without any express or
  381. * implied warranties, including, without limitation, the implied
  382. * warranties of merchantability and fitness for a particular
  383. * purpose.
  384. */