atf_common.h 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182
  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * This is from the ARM TF Project,
  4. * Repository: https://github.com/ARM-software/arm-trusted-firmware.git
  5. * File: include/common/bl_common.h
  6. * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
  7. * reserved.
  8. * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd
  9. */
  10. #ifndef __BL_COMMON_H__
  11. #define __BL_COMMON_H__
  12. #define ATF_PARAM_EP 0x01
  13. #define ATF_PARAM_IMAGE_BINARY 0x02
  14. #define ATF_PARAM_BL31 0x03
  15. #define ATF_VERSION_1 0x01
  16. #define ATF_EP_SECURE 0x0
  17. #define ATF_EP_NON_SECURE 0x1
  18. #define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
  19. (_p)->h.type = (uint8_t)(_type); \
  20. (_p)->h.version = (uint8_t)(_ver); \
  21. (_p)->h.size = (uint16_t)sizeof(*_p); \
  22. (_p)->h.attr = (uint32_t)(_attr) ; \
  23. } while (0)
  24. #define MODE_RW_SHIFT 0x4
  25. #define MODE_RW_MASK 0x1
  26. #define MODE_RW_64 0x0
  27. #define MODE_RW_32 0x1
  28. #define MODE_EL_SHIFT 0x2
  29. #define MODE_EL_MASK 0x3
  30. #define MODE_EL3 0x3
  31. #define MODE_EL2 0x2
  32. #define MODE_EL1 0x1
  33. #define MODE_EL0 0x0
  34. #define MODE_SP_SHIFT 0x0
  35. #define MODE_SP_MASK 0x1
  36. #define MODE_SP_EL0 0x0
  37. #define MODE_SP_ELX 0x1
  38. #define SPSR_DAIF_SHIFT 6
  39. #define SPSR_DAIF_MASK 0x0f
  40. #define SPSR_64(el, sp, daif) \
  41. (MODE_RW_64 << MODE_RW_SHIFT | \
  42. ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
  43. ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
  44. ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
  45. #define SPSR_FIQ (1 << 6)
  46. #define SPSR_IRQ (1 << 7)
  47. #define SPSR_SERROR (1 << 8)
  48. #define SPSR_DEBUG (1 << 9)
  49. #define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
  50. #define DAIF_FIQ_BIT (1<<0)
  51. #define DAIF_IRQ_BIT (1<<1)
  52. #define DAIF_ABT_BIT (1<<2)
  53. #define DAIF_DBG_BIT (1<<3)
  54. #define DISABLE_ALL_EXECPTIONS \
  55. (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
  56. #ifndef __ASSEMBLY__
  57. /*******************************************************************************
  58. * Structure used for telling the next BL how much of a particular type of
  59. * memory is available for its use and how much is already used.
  60. ******************************************************************************/
  61. struct aapcs64_params {
  62. unsigned long arg0;
  63. unsigned long arg1;
  64. unsigned long arg2;
  65. unsigned long arg3;
  66. unsigned long arg4;
  67. unsigned long arg5;
  68. unsigned long arg6;
  69. unsigned long arg7;
  70. };
  71. /***************************************************************************
  72. * This structure provides version information and the size of the
  73. * structure, attributes for the structure it represents
  74. ***************************************************************************/
  75. struct param_header {
  76. uint8_t type; /* type of the structure */
  77. uint8_t version; /* version of this structure */
  78. uint16_t size; /* size of this structure in bytes */
  79. uint32_t attr; /* attributes: unused bits SBZ */
  80. };
  81. /*****************************************************************************
  82. * This structure represents the superset of information needed while
  83. * switching exception levels. The only two mechanisms to do so are
  84. * ERET & SMC. Security state is indicated using bit zero of header
  85. * attribute
  86. * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
  87. * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
  88. * processing SMC to jump to BL31.
  89. *****************************************************************************/
  90. struct entry_point_info {
  91. struct param_header h;
  92. uintptr_t pc;
  93. uint32_t spsr;
  94. struct aapcs64_params args;
  95. };
  96. /*****************************************************************************
  97. * Image info binary provides information from the image loader that
  98. * can be used by the firmware to manage available trusted RAM.
  99. * More advanced firmware image formats can provide additional
  100. * information that enables optimization or greater flexibility in the
  101. * common firmware code
  102. *****************************************************************************/
  103. struct atf_image_info {
  104. struct param_header h;
  105. uintptr_t image_base; /* physical address of base of image */
  106. uint32_t image_size; /* bytes read from image file */
  107. };
  108. /*****************************************************************************
  109. * The image descriptor struct definition.
  110. *****************************************************************************/
  111. struct image_desc {
  112. /* Contains unique image id for the image. */
  113. unsigned int image_id;
  114. /*
  115. * This member contains Image state information.
  116. * Refer IMAGE_STATE_XXX defined above.
  117. */
  118. unsigned int state;
  119. uint32_t copied_size; /* image size copied in blocks */
  120. struct atf_image_info atf_image_info;
  121. struct entry_point_info ep_info;
  122. };
  123. /*******************************************************************************
  124. * This structure represents the superset of information that can be passed to
  125. * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
  126. * populated only if BL2 detects its presence. A pointer to a structure of this
  127. * type should be passed in X0 to BL31's cold boot entrypoint.
  128. *
  129. * Use of this structure and the X0 parameter is not mandatory: the BL31
  130. * platform code can use other mechanisms to provide the necessary information
  131. * about BL32 and BL33 to the common and SPD code.
  132. *
  133. * BL31 image information is mandatory if this structure is used. If either of
  134. * the optional BL32 and BL33 image information is not provided, this is
  135. * indicated by the respective image_info pointers being zero.
  136. ******************************************************************************/
  137. struct bl31_params {
  138. struct param_header h;
  139. struct atf_image_info *bl31_image_info;
  140. struct entry_point_info *bl32_ep_info;
  141. struct atf_image_info *bl32_image_info;
  142. struct entry_point_info *bl33_ep_info;
  143. struct atf_image_info *bl33_image_info;
  144. };
  145. /*******************************************************************************
  146. * This structure represents the superset of information that is passed to
  147. * BL31, e.g. while passing control to it from BL2, bl31_params
  148. * and other platform specific params
  149. ******************************************************************************/
  150. struct bl2_to_bl31_params_mem {
  151. struct bl31_params bl31_params;
  152. struct atf_image_info bl31_image_info;
  153. struct atf_image_info bl32_image_info;
  154. struct atf_image_info bl33_image_info;
  155. struct entry_point_info bl33_ep_info;
  156. struct entry_point_info bl32_ep_info;
  157. struct entry_point_info bl31_ep_info;
  158. };
  159. #endif /*__ASSEMBLY__*/
  160. #endif /* __BL_COMMON_H__ */