SA-1100.h 122 KB

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  1. /*
  2. * FILE SA-1100.h
  3. *
  4. * Version 1.2
  5. * Author Copyright (c) Marc A. Viredaz, 1998
  6. * DEC Western Research Laboratory, Palo Alto, CA
  7. * Date January 1998 (April 1997)
  8. * System StrongARM SA-1100
  9. * Language C or ARM Assembly
  10. * Purpose Definition of constants related to the StrongARM
  11. * SA-1100 microprocessor (Advanced RISC Machine (ARM)
  12. * architecture version 4). This file is based on the
  13. * StrongARM SA-1100 data sheet version 2.2.
  14. *
  15. * Language-specific definitions are selected by the
  16. * macro "LANGUAGE", which should be defined as either
  17. * "C" (default) or "Assembly".
  18. */
  19. #ifndef LANGUAGE
  20. # ifdef __ASSEMBLY__
  21. # define LANGUAGE Assembly
  22. # else
  23. # define LANGUAGE C
  24. # endif
  25. #endif
  26. #ifndef io_p2v
  27. #define io_p2v(PhAdd) (PhAdd)
  28. #endif
  29. #include <asm/arch-sa1100/bitfield.h>
  30. #define C 0
  31. #define Assembly 1
  32. #if LANGUAGE == C
  33. typedef unsigned short Word16 ;
  34. typedef unsigned int Word32 ;
  35. typedef Word32 Word ;
  36. typedef Word Quad [4] ;
  37. typedef void *Address ;
  38. typedef void (*ExcpHndlr) (void) ;
  39. #endif /* LANGUAGE == C */
  40. /*
  41. * Memory
  42. */
  43. #define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */
  44. #define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */
  45. #define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */
  46. /* [byte] */
  47. #define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */
  48. /* [byte] */
  49. #define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */
  50. /* [byte] */
  51. #define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */
  52. /* [byte] */
  53. #define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */
  54. #define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */
  55. #define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */
  56. #define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */
  57. #define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */
  58. #define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */
  59. #define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \
  60. (0x00000000 + (Nb)*StMemBnkSp)
  61. #define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */
  62. #define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */
  63. #define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */
  64. #define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */
  65. #if LANGUAGE == C
  66. typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
  67. #define StMemBnk /* Static Memory Bank [0..3] */ \
  68. ((StMemBnkType *) io_p2v (_StMemBnk (0)))
  69. #define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */
  70. #define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */
  71. #define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */
  72. #define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */
  73. #endif /* LANGUAGE == C */
  74. #define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \
  75. (0xC0000000 + (Nb)*DRAMBnkSp)
  76. #define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */
  77. #define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */
  78. #define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */
  79. #define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */
  80. #if LANGUAGE == C
  81. typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
  82. #define DRAMBnk /* DRAM Bank [0..3] */ \
  83. ((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
  84. #define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */
  85. #define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */
  86. #define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */
  87. #define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */
  88. #endif /* LANGUAGE == C */
  89. #define _ZeroMem 0xE0000000 /* Zero Memory bank */
  90. #if LANGUAGE == C
  91. typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
  92. #define ZeroMem /* Zero Memory bank */ \
  93. (*((ZeroMemType *) io_p2v (_ZeroMem)))
  94. #endif /* LANGUAGE == C */
  95. /*
  96. * Personal Computer Memory Card International Association (PCMCIA) sockets
  97. */
  98. #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
  99. #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
  100. #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
  101. #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
  102. #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
  103. #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
  104. #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
  105. #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
  106. #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
  107. #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
  108. #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
  109. #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
  110. #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
  111. #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
  112. (0x20000000 + (Nb)*PCMCIASp)
  113. #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
  114. #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
  115. (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
  116. #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
  117. (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
  118. #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
  119. #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
  120. #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
  121. #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
  122. #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
  123. #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
  124. #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
  125. #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
  126. #if LANGUAGE == C
  127. typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
  128. typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  129. #define PCMCIA0 /* PCMCIA 0 */ \
  130. (*((PCMCIAType *) io_p2v (_PCMCIA0)))
  131. #define PCMCIA0IO /* PCMCIA 0 I/O */ \
  132. (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
  133. #define PCMCIA0Attr /* PCMCIA 0 Attribute */ \
  134. (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
  135. #define PCMCIA0Mem /* PCMCIA 0 Memory */ \
  136. (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
  137. #define PCMCIA1 /* PCMCIA 1 */ \
  138. (*((PCMCIAType *) io_p2v (_PCMCIA1)))
  139. #define PCMCIA1IO /* PCMCIA 1 I/O */ \
  140. (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
  141. #define PCMCIA1Attr /* PCMCIA 1 Attribute */ \
  142. (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
  143. #define PCMCIA1Mem /* PCMCIA 1 Memory */ \
  144. (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
  145. #endif /* LANGUAGE == C */
  146. /*
  147. * Universal Serial Bus (USB) Device Controller (UDC) control registers
  148. *
  149. * Registers
  150. * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
  151. * Controller (UDC) Control Register (read/write).
  152. * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
  153. * Controller (UDC) Address Register (read/write).
  154. * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
  155. * Controller (UDC) Output Maximum Packet size register
  156. * (read/write).
  157. * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
  158. * Controller (UDC) Input Maximum Packet size register
  159. * (read/write).
  160. * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
  161. * Controller (UDC) Control/Status register end-point 0
  162. * (read/write).
  163. * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
  164. * Controller (UDC) Control/Status register end-point 1
  165. * (output, read/write).
  166. * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
  167. * Controller (UDC) Control/Status register end-point 2
  168. * (input, read/write).
  169. * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
  170. * Controller (UDC) Data register end-point 0
  171. * (read/write).
  172. * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
  173. * Controller (UDC) Write Count register end-point 0
  174. * (read).
  175. * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
  176. * Controller (UDC) Data Register (read/write).
  177. * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
  178. * Controller (UDC) Status Register (read/write).
  179. */
  180. #define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */
  181. #define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */
  182. #define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */
  183. /* Packet size reg. */
  184. #define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */
  185. /* Packet size reg. */
  186. #define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */
  187. /* reg. end-point 0 */
  188. #define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */
  189. /* reg. end-point 1 (output) */
  190. #define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */
  191. /* reg. end-point 2 (input) */
  192. #define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */
  193. /* end-point 0 */
  194. #define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */
  195. /* reg. end-point 0 */
  196. #define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */
  197. #define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */
  198. #if LANGUAGE == C
  199. #define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \
  200. (*((volatile Word *) io_p2v (_Ser0UDCCR)))
  201. #define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \
  202. (*((volatile Word *) io_p2v (_Ser0UDCAR)))
  203. #define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \
  204. /* Packet size reg. */ \
  205. (*((volatile Word *) io_p2v (_Ser0UDCOMP)))
  206. #define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \
  207. /* Packet size reg. */ \
  208. (*((volatile Word *) io_p2v (_Ser0UDCIMP)))
  209. #define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \
  210. /* reg. end-point 0 */ \
  211. (*((volatile Word *) io_p2v (_Ser0UDCCS0)))
  212. #define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \
  213. /* reg. end-point 1 (output) */ \
  214. (*((volatile Word *) io_p2v (_Ser0UDCCS1)))
  215. #define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \
  216. /* reg. end-point 2 (input) */ \
  217. (*((volatile Word *) io_p2v (_Ser0UDCCS2)))
  218. #define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \
  219. /* end-point 0 */ \
  220. (*((volatile Word *) io_p2v (_Ser0UDCD0)))
  221. #define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \
  222. /* reg. end-point 0 */ \
  223. (*((volatile Word *) io_p2v (_Ser0UDCWC)))
  224. #define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \
  225. (*((volatile Word *) io_p2v (_Ser0UDCDR)))
  226. #define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \
  227. (*((volatile Word *) io_p2v (_Ser0UDCSR)))
  228. #endif /* LANGUAGE == C */
  229. #define UDCCR_UDD 0x00000001 /* UDC Disable */
  230. #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
  231. #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
  232. #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
  233. /* (disable) */
  234. #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
  235. /* (disable) */
  236. #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
  237. /* (disable) */
  238. #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
  239. /* (disable) */
  240. #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
  241. #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
  242. #define UDCAR_ADD Fld (7, 0) /* function ADDress */
  243. #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
  244. /* [byte] */
  245. #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
  246. /* [1..256 byte] */ \
  247. (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
  248. #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
  249. /* [byte] */
  250. #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
  251. /* [1..256 byte] */ \
  252. (((Size) - 1) << FShft (UDCIMP_INMAXP))
  253. #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
  254. #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
  255. #define UDCCS0_SST 0x00000004 /* Sent STall */
  256. #define UDCCS0_FST 0x00000008 /* Force STall */
  257. #define UDCCS0_DE 0x00000010 /* Data End */
  258. #define UDCCS0_SE 0x00000020 /* Setup End (read) */
  259. #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
  260. /* (write) */
  261. #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
  262. #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
  263. /* Service request (read) */
  264. #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
  265. #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
  266. #define UDCCS1_SST 0x00000008 /* Sent STall */
  267. #define UDCCS1_FST 0x00000010 /* Force STall */
  268. #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
  269. #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
  270. /* Service request (read) */
  271. #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
  272. #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
  273. #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
  274. #define UDCCS2_SST 0x00000010 /* Sent STall */
  275. #define UDCCS2_FST 0x00000020 /* Force STall */
  276. #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  277. #define UDCWC_WC Fld (4, 0) /* Write Count */
  278. #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  279. #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
  280. #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
  281. #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
  282. #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
  283. #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
  284. #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
  285. /*
  286. * Universal Asynchronous Receiver/Transmitter (UART) control registers
  287. *
  288. * Registers
  289. * Ser1UTCR0 Serial port 1 Universal Asynchronous
  290. * Receiver/Transmitter (UART) Control Register 0
  291. * (read/write).
  292. * Ser1UTCR1 Serial port 1 Universal Asynchronous
  293. * Receiver/Transmitter (UART) Control Register 1
  294. * (read/write).
  295. * Ser1UTCR2 Serial port 1 Universal Asynchronous
  296. * Receiver/Transmitter (UART) Control Register 2
  297. * (read/write).
  298. * Ser1UTCR3 Serial port 1 Universal Asynchronous
  299. * Receiver/Transmitter (UART) Control Register 3
  300. * (read/write).
  301. * Ser1UTDR Serial port 1 Universal Asynchronous
  302. * Receiver/Transmitter (UART) Data Register
  303. * (read/write).
  304. * Ser1UTSR0 Serial port 1 Universal Asynchronous
  305. * Receiver/Transmitter (UART) Status Register 0
  306. * (read/write).
  307. * Ser1UTSR1 Serial port 1 Universal Asynchronous
  308. * Receiver/Transmitter (UART) Status Register 1 (read).
  309. *
  310. * Ser2UTCR0 Serial port 2 Universal Asynchronous
  311. * Receiver/Transmitter (UART) Control Register 0
  312. * (read/write).
  313. * Ser2UTCR1 Serial port 2 Universal Asynchronous
  314. * Receiver/Transmitter (UART) Control Register 1
  315. * (read/write).
  316. * Ser2UTCR2 Serial port 2 Universal Asynchronous
  317. * Receiver/Transmitter (UART) Control Register 2
  318. * (read/write).
  319. * Ser2UTCR3 Serial port 2 Universal Asynchronous
  320. * Receiver/Transmitter (UART) Control Register 3
  321. * (read/write).
  322. * Ser2UTCR4 Serial port 2 Universal Asynchronous
  323. * Receiver/Transmitter (UART) Control Register 4
  324. * (read/write).
  325. * Ser2UTDR Serial port 2 Universal Asynchronous
  326. * Receiver/Transmitter (UART) Data Register
  327. * (read/write).
  328. * Ser2UTSR0 Serial port 2 Universal Asynchronous
  329. * Receiver/Transmitter (UART) Status Register 0
  330. * (read/write).
  331. * Ser2UTSR1 Serial port 2 Universal Asynchronous
  332. * Receiver/Transmitter (UART) Status Register 1 (read).
  333. *
  334. * Ser3UTCR0 Serial port 3 Universal Asynchronous
  335. * Receiver/Transmitter (UART) Control Register 0
  336. * (read/write).
  337. * Ser3UTCR1 Serial port 3 Universal Asynchronous
  338. * Receiver/Transmitter (UART) Control Register 1
  339. * (read/write).
  340. * Ser3UTCR2 Serial port 3 Universal Asynchronous
  341. * Receiver/Transmitter (UART) Control Register 2
  342. * (read/write).
  343. * Ser3UTCR3 Serial port 3 Universal Asynchronous
  344. * Receiver/Transmitter (UART) Control Register 3
  345. * (read/write).
  346. * Ser3UTDR Serial port 3 Universal Asynchronous
  347. * Receiver/Transmitter (UART) Data Register
  348. * (read/write).
  349. * Ser3UTSR0 Serial port 3 Universal Asynchronous
  350. * Receiver/Transmitter (UART) Status Register 0
  351. * (read/write).
  352. * Ser3UTSR1 Serial port 3 Universal Asynchronous
  353. * Receiver/Transmitter (UART) Status Register 1 (read).
  354. *
  355. * Clocks
  356. * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
  357. * or 3.5795 MHz).
  358. * fua, Tua Frequency, period of the UART communication.
  359. */
  360. #define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \
  361. (0x80010000 + ((Nb) - 1)*0x00020000)
  362. #define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \
  363. (0x80010004 + ((Nb) - 1)*0x00020000)
  364. #define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \
  365. (0x80010008 + ((Nb) - 1)*0x00020000)
  366. #define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \
  367. (0x8001000C + ((Nb) - 1)*0x00020000)
  368. #define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \
  369. (0x80010010 + ((Nb) - 1)*0x00020000)
  370. #define _UTDR(Nb) /* UART Data Reg. [1..3] */ \
  371. (0x80010014 + ((Nb) - 1)*0x00020000)
  372. #define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \
  373. (0x8001001C + ((Nb) - 1)*0x00020000)
  374. #define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \
  375. (0x80010020 + ((Nb) - 1)*0x00020000)
  376. #define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
  377. #define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
  378. #define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
  379. #define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
  380. #define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
  381. #define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
  382. #define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
  383. #define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
  384. #define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
  385. #define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
  386. #define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
  387. #define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
  388. #define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
  389. #define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
  390. #define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
  391. #define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
  392. #define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
  393. #define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
  394. #define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
  395. #define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
  396. #define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
  397. #define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
  398. #if LANGUAGE == C
  399. #define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \
  400. (*((volatile Word *) io_p2v (_Ser1UTCR0)))
  401. #define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \
  402. (*((volatile Word *) io_p2v (_Ser1UTCR1)))
  403. #define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \
  404. (*((volatile Word *) io_p2v (_Ser1UTCR2)))
  405. #define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \
  406. (*((volatile Word *) io_p2v (_Ser1UTCR3)))
  407. #define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \
  408. (*((volatile Word *) io_p2v (_Ser1UTDR)))
  409. #define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \
  410. (*((volatile Word *) io_p2v (_Ser1UTSR0)))
  411. #define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \
  412. (*((volatile Word *) io_p2v (_Ser1UTSR1)))
  413. #define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \
  414. (*((volatile Word *) io_p2v (_Ser2UTCR0)))
  415. #define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \
  416. (*((volatile Word *) io_p2v (_Ser2UTCR1)))
  417. #define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \
  418. (*((volatile Word *) io_p2v (_Ser2UTCR2)))
  419. #define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \
  420. (*((volatile Word *) io_p2v (_Ser2UTCR3)))
  421. #define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \
  422. (*((volatile Word *) io_p2v (_Ser2UTCR4)))
  423. #define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \
  424. (*((volatile Word *) io_p2v (_Ser2UTDR)))
  425. #define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \
  426. (*((volatile Word *) io_p2v (_Ser2UTSR0)))
  427. #define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \
  428. (*((volatile Word *) io_p2v (_Ser2UTSR1)))
  429. #define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \
  430. (*((volatile Word *) io_p2v (_Ser3UTCR0)))
  431. #define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \
  432. (*((volatile Word *) io_p2v (_Ser3UTCR1)))
  433. #define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \
  434. (*((volatile Word *) io_p2v (_Ser3UTCR2)))
  435. #define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \
  436. (*((volatile Word *) io_p2v (_Ser3UTCR3)))
  437. #define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \
  438. (*((volatile Word *) io_p2v (_Ser3UTDR)))
  439. #define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \
  440. (*((volatile Word *) io_p2v (_Ser3UTSR0)))
  441. #define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \
  442. (*((volatile Word *) io_p2v (_Ser3UTSR1)))
  443. #elif LANGUAGE == Assembly
  444. #define Ser1UTCR0 ( io_p2v (_Ser1UTCR0))
  445. #define Ser1UTCR1 ( io_p2v (_Ser1UTCR1))
  446. #define Ser1UTCR2 ( io_p2v (_Ser1UTCR2))
  447. #define Ser1UTCR3 ( io_p2v (_Ser1UTCR3))
  448. #define Ser1UTDR ( io_p2v (_Ser1UTDR))
  449. #define Ser1UTSR0 ( io_p2v (_Ser1UTSR0))
  450. #define Ser1UTSR1 ( io_p2v (_Ser1UTSR1))
  451. #define Ser2UTCR0 ( io_p2v (_Ser2UTCR0))
  452. #define Ser2UTCR1 ( io_p2v (_Ser2UTCR1))
  453. #define Ser2UTCR2 ( io_p2v (_Ser2UTCR2))
  454. #define Ser2UTCR3 ( io_p2v (_Ser2UTCR3))
  455. #define Ser2UTCR4 ( io_p2v (_Ser2UTCR4))
  456. #define Ser2UTDR ( io_p2v (_Ser2UTDR))
  457. #define Ser2UTSR0 ( io_p2v (_Ser2UTSR0))
  458. #define Ser2UTSR1 ( io_p2v (_Ser2UTSR1))
  459. #define Ser3UTCR0 ( io_p2v (_Ser3UTCR0))
  460. #define Ser3UTCR1 ( io_p2v (_Ser3UTCR1))
  461. #define Ser3UTCR2 ( io_p2v (_Ser3UTCR2))
  462. #define Ser3UTCR3 ( io_p2v (_Ser3UTCR3))
  463. #define Ser3UTDR ( io_p2v (_Ser3UTDR))
  464. #define Ser3UTSR0 ( io_p2v (_Ser3UTSR0))
  465. #define Ser3UTSR1 ( io_p2v (_Ser3UTSR1))
  466. #endif /* LANGUAGE == C */
  467. #define UTCR0_PE 0x00000001 /* Parity Enable */
  468. #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
  469. #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
  470. #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
  471. #define UTCR0_SBS 0x00000004 /* Stop Bit Select */
  472. #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
  473. #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
  474. #define UTCR0_DSS 0x00000008 /* Data Size Select */
  475. #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
  476. #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
  477. #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
  478. /* (ser. port 1: GPIO [18], */
  479. /* ser. port 3: GPIO [20]) */
  480. #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
  481. #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
  482. #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
  483. #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
  484. #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
  485. #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
  486. #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
  487. (UTCR0_1StpBit + UTCR0_8BitData)
  488. #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
  489. #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
  490. /* fua = fxtl/(16*(BRD[11:0] + 1)) */
  491. /* Tua = 16*(BRD [11:0] + 1)*Txtl */
  492. #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
  493. (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
  494. FShft (UTCR1_BRD))
  495. #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
  496. (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
  497. FShft (UTCR2_BRD))
  498. /* fua = fxtl/(16*Floor (Div/16)) */
  499. /* Tua = 16*Floor (Div/16)*Txtl */
  500. #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
  501. (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
  502. FShft (UTCR1_BRD))
  503. #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
  504. (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
  505. FShft (UTCR2_BRD))
  506. /* fua = fxtl/(16*Ceil (Div/16)) */
  507. /* Tua = 16*Ceil (Div/16)*Txtl */
  508. #define UTCR3_RXE 0x00000001 /* Receive Enable */
  509. #define UTCR3_TXE 0x00000002 /* Transmit Enable */
  510. #define UTCR3_BRK 0x00000004 /* BReaK mode */
  511. #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
  512. /* more Interrupt Enable */
  513. #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
  514. /* Interrupt Enable */
  515. #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
  516. #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
  517. /* TIE, LBM can be set or cleared) */ \
  518. (UTCR3_RXE + UTCR3_TXE)
  519. #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
  520. /* (HP-SIR) modulation Enable */
  521. #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
  522. #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
  523. #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
  524. #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
  525. #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
  526. #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  527. #if 0 /* Hidden receive FIFO bits */
  528. #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
  529. #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
  530. #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
  531. #endif /* 0 */
  532. #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
  533. /* Service request (read) */
  534. #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
  535. /* more Service request (read) */
  536. #define UTSR0_RID 0x00000004 /* Receiver IDle */
  537. #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
  538. #define UTSR0_REB 0x00000010 /* Receive End of Break */
  539. #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
  540. #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
  541. #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
  542. #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
  543. #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
  544. #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
  545. #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
  546. /*
  547. * Synchronous Data Link Controller (SDLC) control registers
  548. *
  549. * Registers
  550. * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
  551. * Control Register 0 (read/write).
  552. * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
  553. * Control Register 1 (read/write).
  554. * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
  555. * Control Register 2 (read/write).
  556. * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
  557. * Control Register 3 (read/write).
  558. * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
  559. * Control Register 4 (read/write).
  560. * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
  561. * Data Register (read/write).
  562. * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
  563. * Status Register 0 (read/write).
  564. * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
  565. * Status Register 1 (read/write).
  566. *
  567. * Clocks
  568. * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
  569. * or 3.5795 MHz).
  570. * fsd, Tsd Frequency, period of the SDLC communication.
  571. */
  572. #define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */
  573. #define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */
  574. #define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */
  575. #define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */
  576. #define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */
  577. #define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */
  578. #define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */
  579. #define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */
  580. #if LANGUAGE == C
  581. #define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \
  582. (*((volatile Word *) io_p2v (_Ser1SDCR0)))
  583. #define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \
  584. (*((volatile Word *) io_p2v (_Ser1SDCR1)))
  585. #define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \
  586. (*((volatile Word *) io_p2v (_Ser1SDCR2)))
  587. #define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \
  588. (*((volatile Word *) io_p2v (_Ser1SDCR3)))
  589. #define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \
  590. (*((volatile Word *) io_p2v (_Ser1SDCR4)))
  591. #define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \
  592. (*((volatile Word *) io_p2v (_Ser1SDDR)))
  593. #define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \
  594. (*((volatile Word *) io_p2v (_Ser1SDSR0)))
  595. #define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \
  596. (*((volatile Word *) io_p2v (_Ser1SDSR1)))
  597. #endif /* LANGUAGE == C */
  598. #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
  599. #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
  600. #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
  601. #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
  602. #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
  603. #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
  604. #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
  605. #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
  606. #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
  607. #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
  608. #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
  609. #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
  610. /* (GPIO [16]) */
  611. #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
  612. #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
  613. #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
  614. #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
  615. #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
  616. #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
  617. #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
  618. #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
  619. #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
  620. /* (GPIO [17]) */
  621. #define SDCR1_TXE 0x00000002 /* Transmit Enable */
  622. #define SDCR1_RXE 0x00000004 /* Receive Enable */
  623. #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
  624. /* more Interrupt Enable */
  625. #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
  626. /* Interrupt Enable */
  627. #define SDCR1_AME 0x00000020 /* Address Match Enable */
  628. #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
  629. #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
  630. #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
  631. #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
  632. #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
  633. #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
  634. #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
  635. /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
  636. /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
  637. #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
  638. (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
  639. FShft (SDCR3_BRD))
  640. #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
  641. (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
  642. FShft (SDCR4_BRD))
  643. /* fsd = fxtl/(16*Floor (Div/16)) */
  644. /* Tsd = 16*Floor (Div/16)*Txtl */
  645. #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
  646. (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
  647. FShft (SDCR3_BRD))
  648. #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
  649. (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
  650. FShft (SDCR4_BRD))
  651. /* fsd = fxtl/(16*Ceil (Div/16)) */
  652. /* Tsd = 16*Ceil (Div/16)*Txtl */
  653. #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  654. #if 0 /* Hidden receive FIFO bits */
  655. #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
  656. #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
  657. #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
  658. #endif /* 0 */
  659. #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
  660. #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
  661. #define SDSR0_RAB 0x00000004 /* Receive ABort */
  662. #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
  663. /* Service request (read) */
  664. #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
  665. /* more Service request (read) */
  666. #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
  667. #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
  668. #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
  669. #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
  670. #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
  671. #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
  672. #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
  673. #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
  674. /*
  675. * High-Speed Serial to Parallel controller (HSSP) control registers
  676. *
  677. * Registers
  678. * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
  679. * controller (HSSP) Control Register 0 (read/write).
  680. * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
  681. * controller (HSSP) Control Register 1 (read/write).
  682. * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
  683. * controller (HSSP) Data Register (read/write).
  684. * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
  685. * controller (HSSP) Status Register 0 (read/write).
  686. * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
  687. * controller (HSSP) Status Register 1 (read).
  688. * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
  689. * controller (HSSP) Control Register 2 (read/write).
  690. * [The HSCR2 register is only implemented in
  691. * versions 2.0 (rev. = 8) and higher of the StrongARM
  692. * SA-1100.]
  693. */
  694. #define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */
  695. #define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */
  696. #define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */
  697. #define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */
  698. #define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */
  699. #define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */
  700. #if LANGUAGE == C
  701. #define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \
  702. (*((volatile Word *) io_p2v (_Ser2HSCR0)))
  703. #define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \
  704. (*((volatile Word *) io_p2v (_Ser2HSCR1)))
  705. #define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \
  706. (*((volatile Word *) io_p2v (_Ser2HSDR)))
  707. #define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \
  708. (*((volatile Word *) io_p2v (_Ser2HSSR0)))
  709. #define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \
  710. (*((volatile Word *) io_p2v (_Ser2HSSR1)))
  711. #define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \
  712. (*((volatile Word *) io_p2v (_Ser2HSCR2)))
  713. #endif /* LANGUAGE == C */
  714. #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
  715. #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
  716. #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
  717. #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
  718. #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
  719. #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
  720. #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
  721. #define HSCR0_TXE 0x00000008 /* Transmit Enable */
  722. #define HSCR0_RXE 0x00000010 /* Receive Enable */
  723. #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
  724. /* more Interrupt Enable */
  725. #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
  726. /* Interrupt Enable */
  727. #define HSCR0_AME 0x00000080 /* Address Match Enable */
  728. #define HSCR1_AMV Fld (8, 0) /* Address Match Value */
  729. #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  730. #if 0 /* Hidden receive FIFO bits */
  731. #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
  732. #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
  733. #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
  734. #endif /* 0 */
  735. #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
  736. #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
  737. #define HSSR0_RAB 0x00000004 /* Receive ABort */
  738. #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
  739. /* Service request (read) */
  740. #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
  741. /* more Service request (read) */
  742. #define HSSR0_FRE 0x00000020 /* receive FRaming Error */
  743. #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
  744. #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
  745. #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
  746. #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
  747. #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
  748. #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
  749. #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
  750. #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
  751. #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
  752. /* (inverted) */
  753. #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
  754. /* (non-inverted) */
  755. #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
  756. #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
  757. /* (inverted) */
  758. #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
  759. /* (non-inverted) */
  760. /*
  761. * Multi-media Communications Port (MCP) control registers
  762. *
  763. * Registers
  764. * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
  765. * Control Register 0 (read/write).
  766. * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
  767. * Data Register 0 (audio, read/write).
  768. * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
  769. * Data Register 1 (telecom, read/write).
  770. * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
  771. * Data Register 2 (CODEC registers, read/write).
  772. * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
  773. * Status Register (read/write).
  774. * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
  775. * Control Register 1 (read/write).
  776. * [The MCCR1 register is only implemented in
  777. * versions 2.0 (rev. = 8) and higher of the StrongARM
  778. * SA-1100.]
  779. *
  780. * Clocks
  781. * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
  782. * 12 MHz, or GPIO [21]).
  783. * faud, Taud Frequency, period of the audio sampling.
  784. * ftcm, Ttcm Frequency, period of the telecom sampling.
  785. */
  786. #define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */
  787. #define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */
  788. /* (audio) */
  789. #define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */
  790. /* (telecom) */
  791. #define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */
  792. /* (CODEC reg.) */
  793. #define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */
  794. #define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */
  795. #if LANGUAGE == C
  796. #define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \
  797. (*((volatile Word *) io_p2v (_Ser4MCCR0)))
  798. #define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \
  799. /* (audio) */ \
  800. (*((volatile Word *) io_p2v (_Ser4MCDR0)))
  801. #define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \
  802. /* (telecom) */ \
  803. (*((volatile Word *) io_p2v (_Ser4MCDR1)))
  804. #define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \
  805. /* (CODEC reg.) */ \
  806. (*((volatile Word *) io_p2v (_Ser4MCDR2)))
  807. #define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \
  808. (*((volatile Word *) io_p2v (_Ser4MCSR)))
  809. #define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \
  810. (*((volatile Word *) io_p2v (_Ser4MCCR1)))
  811. #endif /* LANGUAGE == C */
  812. #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
  813. /* [6..127] */
  814. /* faud = fmc/(32*ASD) */
  815. /* Taud = 32*ASD*Tmc */
  816. #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
  817. /* [192..4064] */ \
  818. ((Div)/32 << FShft (MCCR0_ASD))
  819. /* faud = fmc/(32*Floor (Div/32)) */
  820. /* Taud = 32*Floor (Div/32)*Tmc */
  821. #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
  822. (((Div) + 31)/32 << FShft (MCCR0_ASD))
  823. /* faud = fmc/(32*Ceil (Div/32)) */
  824. /* Taud = 32*Ceil (Div/32)*Tmc */
  825. #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
  826. /* Divisor/32 [16..127] */
  827. /* ftcm = fmc/(32*TSD) */
  828. /* Ttcm = 32*TSD*Tmc */
  829. #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
  830. /* [512..4064] */ \
  831. ((Div)/32 << FShft (MCCR0_TSD))
  832. /* ftcm = fmc/(32*Floor (Div/32)) */
  833. /* Ttcm = 32*Floor (Div/32)*Tmc */
  834. #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
  835. (((Div) + 31)/32 << FShft (MCCR0_TSD))
  836. /* ftcm = fmc/(32*Ceil (Div/32)) */
  837. /* Ttcm = 32*Ceil (Div/32)*Tmc */
  838. #define MCCR0_MCE 0x00010000 /* MCP Enable */
  839. #define MCCR0_ECS 0x00020000 /* External Clock Select */
  840. #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
  841. #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
  842. #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
  843. /* sampling/storing Mode */
  844. #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
  845. #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
  846. #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
  847. /* or less interrupt Enable */
  848. #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
  849. /* or more interrupt Enable */
  850. #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
  851. /* or less interrupt Enable */
  852. #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
  853. /* more interrupt Enable */
  854. #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
  855. #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
  856. #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
  857. (((Div) - 1) << FShft (MCCR0_ECP))
  858. #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
  859. /* FIFOs */
  860. #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
  861. /* FIFOs */
  862. /* receive/transmit CODEC reg. */
  863. /* FIFOs: */
  864. #define MCDR2_DATA Fld (16, 0) /* reg. DATA */
  865. #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
  866. #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
  867. #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
  868. #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
  869. #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
  870. /* or less Service request (read) */
  871. #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
  872. /* more Service request (read) */
  873. #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
  874. /* or less Service request (read) */
  875. #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
  876. /* or more Service request (read) */
  877. #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
  878. #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
  879. #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
  880. #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
  881. #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
  882. /* (read) */
  883. #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
  884. /* (read) */
  885. #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
  886. /* (read) */
  887. #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
  888. /* (read) */
  889. #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
  890. /* (read) */
  891. #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
  892. /* (read) */
  893. #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
  894. #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
  895. #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
  896. #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
  897. /* (11.981 MHz) */
  898. #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
  899. /* (9.585 MHz) */
  900. /*
  901. * Synchronous Serial Port (SSP) control registers
  902. *
  903. * Registers
  904. * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
  905. * Register 0 (read/write).
  906. * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
  907. * Register 1 (read/write).
  908. * [Bits SPO and SP are only implemented in versions 2.0
  909. * (rev. = 8) and higher of the StrongARM SA-1100.]
  910. * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
  911. * Register (read/write).
  912. * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
  913. * Register (read/write).
  914. *
  915. * Clocks
  916. * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
  917. * or 3.5795 MHz).
  918. * fss, Tss Frequency, period of the SSP communication.
  919. */
  920. #define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */
  921. #define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */
  922. #define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */
  923. #define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */
  924. #if LANGUAGE == C
  925. #define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \
  926. (*((volatile Word *) io_p2v (_Ser4SSCR0)))
  927. #define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \
  928. (*((volatile Word *) io_p2v (_Ser4SSCR1)))
  929. #define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \
  930. (*((volatile Word *) io_p2v (_Ser4SSDR)))
  931. #define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \
  932. (*((volatile Word *) io_p2v (_Ser4SSSR)))
  933. #endif /* LANGUAGE == C */
  934. #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
  935. #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
  936. (((Size) - 1) << FShft (SSCR0_DSS))
  937. #define SSCR0_FRF Fld (2, 4) /* FRame Format */
  938. #define SSCR0_Motorola /* Motorola Serial Peripheral */ \
  939. /* Interface (SPI) format */ \
  940. (0 << FShft (SSCR0_FRF))
  941. #define SSCR0_TI /* Texas Instruments Synchronous */ \
  942. /* Serial format */ \
  943. (1 << FShft (SSCR0_FRF))
  944. #define SSCR0_National /* National Microwire format */ \
  945. (2 << FShft (SSCR0_FRF))
  946. #define SSCR0_SSE 0x00000080 /* SSP Enable */
  947. #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
  948. /* fss = fxtl/(2*(SCR + 1)) */
  949. /* Tss = 2*(SCR + 1)*Txtl */
  950. #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
  951. (((Div) - 2)/2 << FShft (SSCR0_SCR))
  952. /* fss = fxtl/(2*Floor (Div/2)) */
  953. /* Tss = 2*Floor (Div/2)*Txtl */
  954. #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
  955. (((Div) - 1)/2 << FShft (SSCR0_SCR))
  956. /* fss = fxtl/(2*Ceil (Div/2)) */
  957. /* Tss = 2*Ceil (Div/2)*Txtl */
  958. #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
  959. /* Interrupt Enable */
  960. #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
  961. /* Interrupt Enable */
  962. #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
  963. #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
  964. #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
  965. #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
  966. #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
  967. #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
  968. /* after frame (SFRM, 1st edge) */
  969. #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
  970. /* after frame (SFRM, 1st edge) */
  971. #define SSCR1_ECS 0x00000020 /* External Clock Select */
  972. #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
  973. #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
  974. #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
  975. #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
  976. #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
  977. #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
  978. #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
  979. /* Service request (read) */
  980. #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
  981. /* Service request (read) */
  982. #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
  983. /*
  984. * Operating System (OS) timer control registers
  985. *
  986. * Registers
  987. * OSMR0 Operating System (OS) timer Match Register 0
  988. * (read/write).
  989. * OSMR1 Operating System (OS) timer Match Register 1
  990. * (read/write).
  991. * OSMR2 Operating System (OS) timer Match Register 2
  992. * (read/write).
  993. * OSMR3 Operating System (OS) timer Match Register 3
  994. * (read/write).
  995. * OSCR Operating System (OS) timer Counter Register
  996. * (read/write).
  997. * OSSR Operating System (OS) timer Status Register
  998. * (read/write).
  999. * OWER Operating System (OS) timer Watch-dog Enable Register
  1000. * (read/write).
  1001. * OIER Operating System (OS) timer Interrupt Enable Register
  1002. * (read/write).
  1003. */
  1004. #define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \
  1005. (0x90000000 + (Nb)*4)
  1006. #define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */
  1007. #define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */
  1008. #define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */
  1009. #define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */
  1010. #define _OSCR 0x90000010 /* OS timer Counter Reg. */
  1011. #define _OSSR 0x90000014 /* OS timer Status Reg. */
  1012. #define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
  1013. #define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */
  1014. #if LANGUAGE == C
  1015. #define OSMR /* OS timer Match Reg. [0..3] */ \
  1016. ((volatile Word *) io_p2v (_OSMR (0)))
  1017. #define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */
  1018. #define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */
  1019. #define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */
  1020. #define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */
  1021. #define OSCR /* OS timer Counter Reg. */ \
  1022. (*((volatile Word *) io_p2v (_OSCR)))
  1023. #define OSSR /* OS timer Status Reg. */ \
  1024. (*((volatile Word *) io_p2v (_OSSR)))
  1025. #define OWER /* OS timer Watch-dog Enable Reg. */ \
  1026. (*((volatile Word *) io_p2v (_OWER)))
  1027. #define OIER /* OS timer Interrupt Enable Reg. */ \
  1028. (*((volatile Word *) io_p2v (_OIER)))
  1029. #endif /* LANGUAGE == C */
  1030. #define OSSR_M(Nb) /* Match detected [0..3] */ \
  1031. (0x00000001 << (Nb))
  1032. #define OSSR_M0 OSSR_M (0) /* Match detected 0 */
  1033. #define OSSR_M1 OSSR_M (1) /* Match detected 1 */
  1034. #define OSSR_M2 OSSR_M (2) /* Match detected 2 */
  1035. #define OSSR_M3 OSSR_M (3) /* Match detected 3 */
  1036. #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
  1037. /* (set only) */
  1038. #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
  1039. (0x00000001 << (Nb))
  1040. #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
  1041. #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
  1042. #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
  1043. #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
  1044. /*
  1045. * Real-Time Clock (RTC) control registers
  1046. *
  1047. * Registers
  1048. * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
  1049. * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
  1050. * RTTR Real-Time Clock (RTC) Trim Register (read/write).
  1051. * RTSR Real-Time Clock (RTC) Status Register (read/write).
  1052. *
  1053. * Clocks
  1054. * frtx, Trtx Frequency, period of the real-time clock crystal
  1055. * (32.768 kHz nominal).
  1056. * frtc, Trtc Frequency, period of the real-time clock counter
  1057. * (1 Hz nominal).
  1058. */
  1059. #define _RTAR 0x90010000 /* RTC Alarm Reg. */
  1060. #define _RCNR 0x90010004 /* RTC CouNt Reg. */
  1061. #define _RTTR 0x90010008 /* RTC Trim Reg. */
  1062. #define _RTSR 0x90010010 /* RTC Status Reg. */
  1063. #if LANGUAGE == C
  1064. #define RTAR /* RTC Alarm Reg. */ \
  1065. (*((volatile Word *) io_p2v (_RTAR)))
  1066. #define RCNR /* RTC CouNt Reg. */ \
  1067. (*((volatile Word *) io_p2v (_RCNR)))
  1068. #define RTTR /* RTC Trim Reg. */ \
  1069. (*((volatile Word *) io_p2v (_RTTR)))
  1070. #define RTSR /* RTC Status Reg. */ \
  1071. (*((volatile Word *) io_p2v (_RTSR)))
  1072. #endif /* LANGUAGE == C */
  1073. #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
  1074. #define RTTR_D Fld (10, 16) /* trim Delete count */
  1075. /* frtc = (1023*(C + 1) - D)*frtx/ */
  1076. /* (1023*(C + 1)^2) */
  1077. /* Trtc = (1023*(C + 1)^2)*Trtx/ */
  1078. /* (1023*(C + 1) - D) */
  1079. #define RTSR_AL 0x00000001 /* ALarm detected */
  1080. #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
  1081. #define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */
  1082. #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
  1083. /*
  1084. * Power Manager (PM) control registers
  1085. *
  1086. * Registers
  1087. * PMCR Power Manager (PM) Control Register (read/write).
  1088. * PSSR Power Manager (PM) Sleep Status Register (read/write).
  1089. * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
  1090. * PWER Power Manager (PM) Wake-up Enable Register
  1091. * (read/write).
  1092. * PCFR Power Manager (PM) general ConFiguration Register
  1093. * (read/write).
  1094. * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
  1095. * Configuration Register (read/write).
  1096. * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
  1097. * Sleep state Register (read/write, see GPIO pins).
  1098. * POSR Power Manager (PM) Oscillator Status Register (read).
  1099. *
  1100. * Clocks
  1101. * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
  1102. * or 3.5795 MHz).
  1103. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1104. */
  1105. #define _PMCR 0x90020000 /* PM Control Reg. */
  1106. #define _PSSR 0x90020004 /* PM Sleep Status Reg. */
  1107. #define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
  1108. #define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
  1109. #define _PCFR 0x90020010 /* PM general ConFiguration Reg. */
  1110. #define _PPCR 0x90020014 /* PM PLL Configuration Reg. */
  1111. #define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */
  1112. #define _POSR 0x9002001C /* PM Oscillator Status Reg. */
  1113. #if LANGUAGE == C
  1114. #define PMCR /* PM Control Reg. */ \
  1115. (*((volatile Word *) io_p2v (_PMCR)))
  1116. #define PSSR /* PM Sleep Status Reg. */ \
  1117. (*((volatile Word *) io_p2v (_PSSR)))
  1118. #define PSPR /* PM Scratch-Pad Reg. */ \
  1119. (*((volatile Word *) io_p2v (_PSPR)))
  1120. #define PWER /* PM Wake-up Enable Reg. */ \
  1121. (*((volatile Word *) io_p2v (_PWER)))
  1122. #define PCFR /* PM general ConFiguration Reg. */ \
  1123. (*((volatile Word *) io_p2v (_PCFR)))
  1124. #define PPCR /* PM PLL Configuration Reg. */ \
  1125. (*((volatile Word *) io_p2v (_PPCR)))
  1126. #define PGSR /* PM GPIO Sleep state Reg. */ \
  1127. (*((volatile Word *) io_p2v (_PGSR)))
  1128. #define POSR /* PM Oscillator Status Reg. */ \
  1129. (*((volatile Word *) io_p2v (_POSR)))
  1130. #elif LANGUAGE == Assembly
  1131. #define PMCR (io_p2v (_PMCR))
  1132. #define PSSR (io_p2v (_PSSR))
  1133. #define PSPR (io_p2v (_PSPR))
  1134. #define PWER (io_p2v (_PWER))
  1135. #define PCFR (io_p2v (_PCFR))
  1136. #define PPCR (io_p2v (_PPCR))
  1137. #define PGSR (io_p2v (_PGSR))
  1138. #define POSR (io_p2v (_POSR))
  1139. #endif /* LANGUAGE == C */
  1140. #define PMCR_SF 0x00000001 /* Sleep Force (set only) */
  1141. #define PSSR_SS 0x00000001 /* Software Sleep */
  1142. #define PSSR_BFS 0x00000002 /* Battery Fault Status */
  1143. /* (BATT_FAULT) */
  1144. #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
  1145. #define PSSR_DH 0x00000008 /* DRAM control Hold */
  1146. #define PSSR_PH 0x00000010 /* Peripheral control Hold */
  1147. #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
  1148. #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
  1149. #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
  1150. #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
  1151. #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
  1152. #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
  1153. #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
  1154. #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
  1155. #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
  1156. #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
  1157. #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
  1158. #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
  1159. #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
  1160. #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
  1161. #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
  1162. #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
  1163. #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
  1164. #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
  1165. #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
  1166. #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
  1167. #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
  1168. #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
  1169. #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
  1170. #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
  1171. #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
  1172. #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
  1173. #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
  1174. #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
  1175. #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
  1176. #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
  1177. #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
  1178. #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
  1179. #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
  1180. #define PCFR_FP 0x00000002 /* Float PCMCIA pins */
  1181. #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
  1182. #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
  1183. #define PCFR_FS 0x00000004 /* Float Static memory pins */
  1184. #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
  1185. #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
  1186. #define PCFR_FO 0x00000008 /* Force RTC oscillator */
  1187. /* (32.768 kHz) enable On */
  1188. #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
  1189. #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
  1190. (0x00 << FShft (PPCR_CCF))
  1191. #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
  1192. (0x01 << FShft (PPCR_CCF))
  1193. #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
  1194. (0x02 << FShft (PPCR_CCF))
  1195. #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
  1196. (0x03 << FShft (PPCR_CCF))
  1197. #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
  1198. (0x04 << FShft (PPCR_CCF))
  1199. #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
  1200. (0x05 << FShft (PPCR_CCF))
  1201. #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
  1202. (0x06 << FShft (PPCR_CCF))
  1203. #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
  1204. (0x07 << FShft (PPCR_CCF))
  1205. #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
  1206. (0x08 << FShft (PPCR_CCF))
  1207. #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
  1208. (0x09 << FShft (PPCR_CCF))
  1209. #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
  1210. (0x0A << FShft (PPCR_CCF))
  1211. #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
  1212. (0x0B << FShft (PPCR_CCF))
  1213. #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
  1214. (0x0C << FShft (PPCR_CCF))
  1215. #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
  1216. (0x0D << FShft (PPCR_CCF))
  1217. #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
  1218. (0x0E << FShft (PPCR_CCF))
  1219. #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
  1220. (0x0F << FShft (PPCR_CCF))
  1221. /* 3.6864 MHz crystal (fxtl): */
  1222. #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
  1223. #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
  1224. #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
  1225. #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
  1226. #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
  1227. #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
  1228. #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
  1229. #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
  1230. #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
  1231. #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
  1232. #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
  1233. #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
  1234. #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
  1235. #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
  1236. #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
  1237. #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
  1238. /* 3.5795 MHz crystal (fxtl): */
  1239. #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
  1240. #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
  1241. #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
  1242. #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
  1243. #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
  1244. #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
  1245. #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
  1246. #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
  1247. #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
  1248. #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
  1249. #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
  1250. #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
  1251. #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
  1252. #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
  1253. #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
  1254. #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
  1255. #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
  1256. /*
  1257. * Reset Controller (RC) control registers
  1258. *
  1259. * Registers
  1260. * RSRR Reset Controller (RC) Software Reset Register
  1261. * (read/write).
  1262. * RCSR Reset Controller (RC) Status Register (read/write).
  1263. */
  1264. #define _RSRR 0x90030000 /* RC Software Reset Reg. */
  1265. #define _RCSR 0x90030004 /* RC Status Reg. */
  1266. #if LANGUAGE == C
  1267. #define RSRR /* RC Software Reset Reg. */ \
  1268. (*((volatile Word *) io_p2v (_RSRR)))
  1269. #define RCSR /* RC Status Reg. */ \
  1270. (*((volatile Word *) io_p2v (_RCSR)))
  1271. #endif /* LANGUAGE == C */
  1272. #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
  1273. #define RCSR_HWR 0x00000001 /* HardWare Reset */
  1274. #define RCSR_SWR 0x00000002 /* SoftWare Reset */
  1275. #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
  1276. #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
  1277. /*
  1278. * Test unit control registers
  1279. *
  1280. * Registers
  1281. * TUCR Test Unit Control Register (read/write).
  1282. */
  1283. #define _TUCR 0x90030008 /* Test Unit Control Reg. */
  1284. #if LANGUAGE == C
  1285. #define TUCR /* Test Unit Control Reg. */ \
  1286. (*((volatile Word *) io_p2v (_TUCR)))
  1287. #endif /* LANGUAGE == C */
  1288. #define TUCR_TIC 0x00000040 /* TIC mode */
  1289. #define TUCR_TTST 0x00000080 /* Trim TeST mode */
  1290. #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
  1291. /* Check */
  1292. #define TUCR_PMD 0x00000200 /* Power Management Disable */
  1293. #define TUCR_MR 0x00000400 /* Memory Request mode */
  1294. #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
  1295. #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
  1296. /* grant (MBGNT) on GPIO [22:21] */
  1297. #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
  1298. #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
  1299. #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
  1300. #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
  1301. #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
  1302. #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
  1303. #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
  1304. (0 << FShft (TUCR_TSEL))
  1305. #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
  1306. (1 << FShft (TUCR_TSEL))
  1307. #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
  1308. (2 << FShft (TUCR_TSEL))
  1309. #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
  1310. (3 << FShft (TUCR_TSEL))
  1311. #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
  1312. /* Clocks on GPIO [26:27] */ \
  1313. (4 << FShft (TUCR_TSEL))
  1314. #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
  1315. /* (Alternative) */ \
  1316. (5 << FShft (TUCR_TSEL))
  1317. #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
  1318. (6 << FShft (TUCR_TSEL))
  1319. #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
  1320. (7 << FShft (TUCR_TSEL))
  1321. /*
  1322. * General-Purpose Input/Output (GPIO) control registers
  1323. *
  1324. * Registers
  1325. * GPLR General-Purpose Input/Output (GPIO) Pin Level
  1326. * Register (read).
  1327. * GPDR General-Purpose Input/Output (GPIO) Pin Direction
  1328. * Register (read/write).
  1329. * GPSR General-Purpose Input/Output (GPIO) Pin output Set
  1330. * Register (write).
  1331. * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
  1332. * Register (write).
  1333. * GRER General-Purpose Input/Output (GPIO) Rising-Edge
  1334. * detect Register (read/write).
  1335. * GFER General-Purpose Input/Output (GPIO) Falling-Edge
  1336. * detect Register (read/write).
  1337. * GEDR General-Purpose Input/Output (GPIO) Edge Detect
  1338. * status Register (read/write).
  1339. * GAFR General-Purpose Input/Output (GPIO) Alternate
  1340. * Function Register (read/write).
  1341. *
  1342. * Clock
  1343. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1344. */
  1345. #define _GPLR 0x90040000 /* GPIO Pin Level Reg. */
  1346. #define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */
  1347. #define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */
  1348. #define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */
  1349. #define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
  1350. #define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
  1351. #define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */
  1352. #define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */
  1353. #if LANGUAGE == C
  1354. #define GPLR /* GPIO Pin Level Reg. */ \
  1355. (*((volatile Word *) io_p2v (_GPLR)))
  1356. #define GPDR /* GPIO Pin Direction Reg. */ \
  1357. (*((volatile Word *) io_p2v (_GPDR)))
  1358. #define GPSR /* GPIO Pin output Set Reg. */ \
  1359. (*((volatile Word *) io_p2v (_GPSR)))
  1360. #define GPCR /* GPIO Pin output Clear Reg. */ \
  1361. (*((volatile Word *) io_p2v (_GPCR)))
  1362. #define GRER /* GPIO Rising-Edge detect Reg. */ \
  1363. (*((volatile Word *) io_p2v (_GRER)))
  1364. #define GFER /* GPIO Falling-Edge detect Reg. */ \
  1365. (*((volatile Word *) io_p2v (_GFER)))
  1366. #define GEDR /* GPIO Edge Detect status Reg. */ \
  1367. (*((volatile Word *) io_p2v (_GEDR)))
  1368. #define GAFR /* GPIO Alternate Function Reg. */ \
  1369. (*((volatile Word *) io_p2v (_GAFR)))
  1370. #elif LANGUAGE == Assembly
  1371. #define GPLR (io_p2v (_GPLR))
  1372. #define GPDR (io_p2v (_GPDR))
  1373. #define GPSR (io_p2v (_GPSR))
  1374. #define GPCR (io_p2v (_GPCR))
  1375. #define GRER (io_p2v (_GRER))
  1376. #define GFER (io_p2v (_GFER))
  1377. #define GEDR (io_p2v (_GEDR))
  1378. #define GAFR (io_p2v (_GAFR))
  1379. #endif /* LANGUAGE == C */
  1380. #define GPIO_MIN (0)
  1381. #define GPIO_MAX (27)
  1382. #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
  1383. (0x00000001 << (Nb))
  1384. #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
  1385. #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
  1386. #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
  1387. #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
  1388. #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
  1389. #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
  1390. #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
  1391. #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
  1392. #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
  1393. #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
  1394. #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
  1395. #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
  1396. #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
  1397. #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
  1398. #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
  1399. #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
  1400. #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
  1401. #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
  1402. #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
  1403. #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
  1404. #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
  1405. #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
  1406. #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
  1407. #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
  1408. #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
  1409. #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
  1410. #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
  1411. #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
  1412. #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
  1413. GPIO_GPIO ((Nb) - 6)
  1414. #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
  1415. #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
  1416. #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
  1417. #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
  1418. #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
  1419. #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
  1420. #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
  1421. #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
  1422. /* ser. port 4: */
  1423. #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
  1424. #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
  1425. #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
  1426. #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
  1427. /* ser. port 1: */
  1428. #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
  1429. #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
  1430. #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
  1431. #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
  1432. #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
  1433. /* ser. port 4: */
  1434. #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
  1435. /* ser. port 3: */
  1436. #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
  1437. /* ser. port 4: */
  1438. #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
  1439. /* test controller: */
  1440. #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
  1441. #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
  1442. #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
  1443. #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
  1444. #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
  1445. #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
  1446. #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
  1447. #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
  1448. #define GPDR_In 0 /* Input */
  1449. #define GPDR_Out 1 /* Output */
  1450. /*
  1451. * Interrupt Controller (IC) control registers
  1452. *
  1453. * Registers
  1454. * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
  1455. * Pending register (read).
  1456. * ICMR Interrupt Controller (IC) Mask Register (read/write).
  1457. * ICLR Interrupt Controller (IC) Level Register (read/write).
  1458. * ICCR Interrupt Controller (IC) Control Register
  1459. * (read/write).
  1460. * [The ICCR register is only implemented in versions 2.0
  1461. * (rev. = 8) and higher of the StrongARM SA-1100.]
  1462. * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
  1463. * (FIQ) Pending register (read).
  1464. * ICPR Interrupt Controller (IC) Pending Register (read).
  1465. * [The ICPR register is active low (inverted) in
  1466. * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
  1467. * StrongARM SA-1100, it is active high (non-inverted) in
  1468. * versions 2.0 (rev. = 8) and higher.]
  1469. */
  1470. #define _ICIP 0x90050000 /* IC IRQ Pending reg. */
  1471. #define _ICMR 0x90050004 /* IC Mask Reg. */
  1472. #define _ICLR 0x90050008 /* IC Level Reg. */
  1473. #define _ICCR 0x9005000C /* IC Control Reg. */
  1474. #define _ICFP 0x90050010 /* IC FIQ Pending reg. */
  1475. #define _ICPR 0x90050020 /* IC Pending Reg. */
  1476. #if LANGUAGE == C
  1477. #define ICIP /* IC IRQ Pending reg. */ \
  1478. (*((volatile Word *) io_p2v (_ICIP)))
  1479. #define ICMR /* IC Mask Reg. */ \
  1480. (*((volatile Word *) io_p2v (_ICMR)))
  1481. #define ICLR /* IC Level Reg. */ \
  1482. (*((volatile Word *) io_p2v (_ICLR)))
  1483. #define ICCR /* IC Control Reg. */ \
  1484. (*((volatile Word *) io_p2v (_ICCR)))
  1485. #define ICFP /* IC FIQ Pending reg. */ \
  1486. (*((volatile Word *) io_p2v (_ICFP)))
  1487. #define ICPR /* IC Pending Reg. */ \
  1488. (*((volatile Word *) io_p2v (_ICPR)))
  1489. #endif /* LANGUAGE == C */
  1490. #define IC_GPIO(Nb) /* GPIO [0..10] */ \
  1491. (0x00000001 << (Nb))
  1492. #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
  1493. #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
  1494. #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
  1495. #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
  1496. #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
  1497. #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
  1498. #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
  1499. #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
  1500. #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
  1501. #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
  1502. #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
  1503. #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
  1504. #define IC_LCD 0x00001000 /* LCD controller */
  1505. #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
  1506. #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
  1507. #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
  1508. #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
  1509. #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
  1510. #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
  1511. #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
  1512. #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
  1513. (0x00100000 << (Nb))
  1514. #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
  1515. #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
  1516. #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
  1517. #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
  1518. #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
  1519. #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
  1520. #define IC_OST(Nb) /* OS Timer match [0..3] */ \
  1521. (0x04000000 << (Nb))
  1522. #define IC_OST0 IC_OST (0) /* OS Timer match 0 */
  1523. #define IC_OST1 IC_OST (1) /* OS Timer match 1 */
  1524. #define IC_OST2 IC_OST (2) /* OS Timer match 2 */
  1525. #define IC_OST3 IC_OST (3) /* OS Timer match 3 */
  1526. #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
  1527. #define IC_RTCAlrm 0x80000000 /* RTC Alarm */
  1528. #define ICLR_IRQ 0 /* Interrupt ReQuest */
  1529. #define ICLR_FIQ 1 /* Fast Interrupt reQuest */
  1530. #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
  1531. /* Mask */
  1532. #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
  1533. /* (ICMR ignored) */
  1534. #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
  1535. /* enable (ICMR used) */
  1536. /*
  1537. * Peripheral Pin Controller (PPC) control registers
  1538. *
  1539. * Registers
  1540. * PPDR Peripheral Pin Controller (PPC) Pin Direction
  1541. * Register (read/write).
  1542. * PPSR Peripheral Pin Controller (PPC) Pin State Register
  1543. * (read/write).
  1544. * PPAR Peripheral Pin Controller (PPC) Pin Assignment
  1545. * Register (read/write).
  1546. * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
  1547. * Direction Register (read/write).
  1548. * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
  1549. * (read).
  1550. */
  1551. #define _PPDR 0x90060000 /* PPC Pin Direction Reg. */
  1552. #define _PPSR 0x90060004 /* PPC Pin State Reg. */
  1553. #define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */
  1554. #define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
  1555. /* Reg. */
  1556. #define _PPFR 0x90060010 /* PPC Pin Flag Reg. */
  1557. #if LANGUAGE == C
  1558. #define PPDR /* PPC Pin Direction Reg. */ \
  1559. (*((volatile Word *) io_p2v (_PPDR)))
  1560. #define PPSR /* PPC Pin State Reg. */ \
  1561. (*((volatile Word *) io_p2v (_PPSR)))
  1562. #define PPAR /* PPC Pin Assignment Reg. */ \
  1563. (*((volatile Word *) io_p2v (_PPAR)))
  1564. #define PSDR /* PPC Sleep-mode pin Direction */ \
  1565. /* Reg. */ \
  1566. (*((volatile Word *) io_p2v (_PSDR)))
  1567. #define PPFR /* PPC Pin Flag Reg. */ \
  1568. (*((volatile Word *) io_p2v (_PPFR)))
  1569. #endif /* LANGUAGE == C */
  1570. #define PPC_LDD(Nb) /* LCD Data [0..7] */ \
  1571. (0x00000001 << (Nb))
  1572. #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
  1573. #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
  1574. #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
  1575. #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
  1576. #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
  1577. #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
  1578. #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
  1579. #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
  1580. #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
  1581. #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
  1582. #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
  1583. #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
  1584. /* ser. port 1: */
  1585. #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
  1586. #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
  1587. /* ser. port 2: */
  1588. #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
  1589. #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
  1590. /* ser. port 3: */
  1591. #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
  1592. #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
  1593. /* ser. port 4: */
  1594. #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
  1595. #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
  1596. #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
  1597. #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
  1598. #define PPDR_In 0 /* Input */
  1599. #define PPDR_Out 1 /* Output */
  1600. /* ser. port 1: */
  1601. #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
  1602. #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
  1603. #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
  1604. /* ser. port 4: */
  1605. #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
  1606. #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
  1607. /* & SFRM_C */
  1608. #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
  1609. #define PSDR_OutL 0 /* Output Low in sleep mode */
  1610. #define PSDR_Flt 1 /* Floating (input) in sleep mode */
  1611. #define PPFR_LCD 0x00000001 /* LCD controller */
  1612. #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
  1613. #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
  1614. #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
  1615. #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
  1616. #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
  1617. #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
  1618. #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
  1619. #define PPFR_PerEn 0 /* Peripheral Enabled */
  1620. #define PPFR_PPCEn 1 /* PPC Enabled */
  1621. /*
  1622. * Dynamic Random-Access Memory (DRAM) control registers
  1623. *
  1624. * Registers
  1625. * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
  1626. * CoNFiGuration register (read/write).
  1627. * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
  1628. * Column Address Strobe (CAS) shift register 0
  1629. * (read/write).
  1630. * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
  1631. * Column Address Strobe (CAS) shift register 1
  1632. * (read/write).
  1633. * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
  1634. * Column Address Strobe (CAS) shift register 2
  1635. * (read/write).
  1636. *
  1637. * Clocks
  1638. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1639. * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
  1640. * fcas, Tcas Frequency, period of the DRAM CAS shift registers.
  1641. */
  1642. /* Memory system: */
  1643. #define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */
  1644. #define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \
  1645. (0xA0000004 + (Nb)*4)
  1646. #define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */
  1647. #define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */
  1648. #define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */
  1649. #if LANGUAGE == C
  1650. /* Memory system: */
  1651. #define MDCNFG /* DRAM CoNFiGuration reg. */ \
  1652. (*((volatile Word *) io_p2v (_MDCNFG)))
  1653. #define MDCAS /* DRAM CAS shift reg. [0..3] */ \
  1654. ((volatile Word *) io_p2v (_MDCAS (0)))
  1655. #define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */
  1656. #define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */
  1657. #define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */
  1658. #elif LANGUAGE == Assembly
  1659. #define MDCNFG (io_p2v(_MDCNFG))
  1660. #endif /* LANGUAGE == C */
  1661. /* SA1100 MDCNFG values */
  1662. #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
  1663. (0x00000001 << (Nb))
  1664. #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
  1665. #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
  1666. #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
  1667. #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
  1668. #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
  1669. #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
  1670. (((Add) - 9) << FShft (MDCNFG_DRAC))
  1671. #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
  1672. /* (fcas = fcpu/2) */
  1673. #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
  1674. #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
  1675. (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
  1676. #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
  1677. (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
  1678. #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
  1679. #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
  1680. (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
  1681. #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
  1682. (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
  1683. #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
  1684. #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
  1685. ((Tcpu) << FShft (MDCNFG_TDL))
  1686. #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
  1687. /* [Tmem] */
  1688. #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
  1689. /* [0..262136 Tcpu] */ \
  1690. ((Tcpu)/8 << FShft (MDCNFG_DRI))
  1691. /* SA1110 MDCNFG values */
  1692. #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
  1693. #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
  1694. #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
  1695. #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
  1696. #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
  1697. /* bank 0/1 */
  1698. #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
  1699. #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
  1700. #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
  1701. /* deassertion 0/1 */
  1702. #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
  1703. #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
  1704. #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
  1705. #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
  1706. #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
  1707. #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
  1708. /* bank 0/1 */
  1709. #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
  1710. #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
  1711. #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
  1712. /* deassertion 0/1 */
  1713. #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
  1714. /*
  1715. * Static memory control registers
  1716. *
  1717. * Registers
  1718. * MSC0 Memory system: Static memory Control register 0
  1719. * (read/write).
  1720. * MSC1 Memory system: Static memory Control register 1
  1721. * (read/write).
  1722. *
  1723. * Clocks
  1724. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1725. * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
  1726. */
  1727. /* Memory system: */
  1728. #define _MSC(Nb) /* Static memory Control reg. */ \
  1729. /* [0..1] */ \
  1730. (0xA0000010 + (Nb)*4)
  1731. #define _MSC0 _MSC (0) /* Static memory Control reg. 0 */
  1732. #define _MSC1 _MSC (1) /* Static memory Control reg. 1 */
  1733. #define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */
  1734. #if LANGUAGE == C
  1735. /* Memory system: */
  1736. #define MSC /* Static memory Control reg. */ \
  1737. /* [0..1] */ \
  1738. ((volatile Word *) io_p2v (_MSC (0)))
  1739. #define MSC0 (MSC [0]) /* Static memory Control reg. 0 */
  1740. #define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
  1741. #define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */
  1742. #elif LANGUAGE == Assembly
  1743. #define MSC0 io_p2v(0xa0000010)
  1744. #define MSC1 io_p2v(0xa0000014)
  1745. #define MSC2 io_p2v(0xa000002c)
  1746. #endif /* LANGUAGE == C */
  1747. #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
  1748. Fld (16, ((Nb) Modulo 2)*16)
  1749. #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
  1750. #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
  1751. #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
  1752. #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
  1753. #define MSC_RT Fld (2, 0) /* ROM/static memory Type */
  1754. #define MSC_NonBrst /* Non-Burst static memory */ \
  1755. (0 << FShft (MSC_RT))
  1756. #define MSC_SRAM /* 32-bit byte-writable SRAM */ \
  1757. (1 << FShft (MSC_RT))
  1758. #define MSC_Brst4 /* Burst-of-4 static memory */ \
  1759. (2 << FShft (MSC_RT))
  1760. #define MSC_Brst8 /* Burst-of-8 static memory */ \
  1761. (3 << FShft (MSC_RT))
  1762. #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
  1763. #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
  1764. #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
  1765. #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
  1766. /* First access - 1(.5) [Tmem] */
  1767. #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
  1768. /* static memory) [3..65 Tcpu] */ \
  1769. ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
  1770. #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
  1771. ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
  1772. #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
  1773. /* static memory) [2..64 Tcpu] */ \
  1774. ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
  1775. #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
  1776. ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
  1777. #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
  1778. /* Next access - 1 [Tmem] */
  1779. #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
  1780. /* static memory) [2..64 Tcpu] */ \
  1781. ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
  1782. #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
  1783. ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
  1784. #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
  1785. /* static memory) [2..64 Tcpu] */ \
  1786. ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
  1787. #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
  1788. ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
  1789. #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
  1790. /* time/2 [Tmem] */
  1791. #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
  1792. (((Tcpu)/4) << FShft (MSC_RRR))
  1793. #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
  1794. ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
  1795. /*
  1796. * Personal Computer Memory Card International Association (PCMCIA) control
  1797. * register
  1798. *
  1799. * Register
  1800. * MECR Memory system: Expansion memory bus (PCMCIA)
  1801. * Configuration Register (read/write).
  1802. *
  1803. * Clocks
  1804. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1805. * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
  1806. * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
  1807. */
  1808. /* Memory system: */
  1809. #define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */
  1810. /* Configuration Reg. */
  1811. #if LANGUAGE == C
  1812. /* Memory system: */
  1813. #define MECR /* Expansion memory bus (PCMCIA) */ \
  1814. /* Configuration Reg. */ \
  1815. (*((volatile Word *) io_p2v (_MECR)))
  1816. #endif /* LANGUAGE == C */
  1817. #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
  1818. Fld (15, (Nb)*16)
  1819. #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
  1820. #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
  1821. #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
  1822. #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
  1823. ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
  1824. #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
  1825. ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
  1826. #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
  1827. /* [Tmem] */
  1828. #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
  1829. ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
  1830. #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
  1831. ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
  1832. #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
  1833. #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
  1834. ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
  1835. #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
  1836. ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
  1837. /*
  1838. * On SA1110 only
  1839. */
  1840. #define _MDREFR 0xA000001C
  1841. #if LANGUAGE == C
  1842. /* Memory system: */
  1843. #define MDREFR \
  1844. (*((volatile Word *) io_p2v (_MDREFR)))
  1845. #elif LANGUAGE == Assembly
  1846. #define MDREFR (io_p2v(_MDREFR))
  1847. #endif /* LANGUAGE == C */
  1848. #define MDREFR_TRASR Fld (4, 0)
  1849. #define MDREFR_DRI Fld (12, 4)
  1850. #define MDREFR_E0PIN (1 << 16)
  1851. #define MDREFR_K0RUN (1 << 17)
  1852. #define MDREFR_K0DB2 (1 << 18)
  1853. #define MDREFR_E1PIN (1 << 20)
  1854. #define MDREFR_K1RUN (1 << 21)
  1855. #define MDREFR_K1DB2 (1 << 22)
  1856. #define MDREFR_K2RUN (1 << 25)
  1857. #define MDREFR_K2DB2 (1 << 26)
  1858. #define MDREFR_EAPD (1 << 28)
  1859. #define MDREFR_KAPD (1 << 29)
  1860. #define MDREFR_SLFRSH (1 << 31)
  1861. /*
  1862. * Direct Memory Access (DMA) control registers
  1863. *
  1864. * Registers
  1865. * DDAR0 Direct Memory Access (DMA) Device Address Register
  1866. * channel 0 (read/write).
  1867. * DCSR0 Direct Memory Access (DMA) Control and Status
  1868. * Register channel 0 (read/write).
  1869. * DBSA0 Direct Memory Access (DMA) Buffer Start address
  1870. * register A channel 0 (read/write).
  1871. * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
  1872. * register A channel 0 (read/write).
  1873. * DBSB0 Direct Memory Access (DMA) Buffer Start address
  1874. * register B channel 0 (read/write).
  1875. * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
  1876. * register B channel 0 (read/write).
  1877. *
  1878. * DDAR1 Direct Memory Access (DMA) Device Address Register
  1879. * channel 1 (read/write).
  1880. * DCSR1 Direct Memory Access (DMA) Control and Status
  1881. * Register channel 1 (read/write).
  1882. * DBSA1 Direct Memory Access (DMA) Buffer Start address
  1883. * register A channel 1 (read/write).
  1884. * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
  1885. * register A channel 1 (read/write).
  1886. * DBSB1 Direct Memory Access (DMA) Buffer Start address
  1887. * register B channel 1 (read/write).
  1888. * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
  1889. * register B channel 1 (read/write).
  1890. *
  1891. * DDAR2 Direct Memory Access (DMA) Device Address Register
  1892. * channel 2 (read/write).
  1893. * DCSR2 Direct Memory Access (DMA) Control and Status
  1894. * Register channel 2 (read/write).
  1895. * DBSA2 Direct Memory Access (DMA) Buffer Start address
  1896. * register A channel 2 (read/write).
  1897. * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
  1898. * register A channel 2 (read/write).
  1899. * DBSB2 Direct Memory Access (DMA) Buffer Start address
  1900. * register B channel 2 (read/write).
  1901. * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
  1902. * register B channel 2 (read/write).
  1903. *
  1904. * DDAR3 Direct Memory Access (DMA) Device Address Register
  1905. * channel 3 (read/write).
  1906. * DCSR3 Direct Memory Access (DMA) Control and Status
  1907. * Register channel 3 (read/write).
  1908. * DBSA3 Direct Memory Access (DMA) Buffer Start address
  1909. * register A channel 3 (read/write).
  1910. * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
  1911. * register A channel 3 (read/write).
  1912. * DBSB3 Direct Memory Access (DMA) Buffer Start address
  1913. * register B channel 3 (read/write).
  1914. * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
  1915. * register B channel 3 (read/write).
  1916. *
  1917. * DDAR4 Direct Memory Access (DMA) Device Address Register
  1918. * channel 4 (read/write).
  1919. * DCSR4 Direct Memory Access (DMA) Control and Status
  1920. * Register channel 4 (read/write).
  1921. * DBSA4 Direct Memory Access (DMA) Buffer Start address
  1922. * register A channel 4 (read/write).
  1923. * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
  1924. * register A channel 4 (read/write).
  1925. * DBSB4 Direct Memory Access (DMA) Buffer Start address
  1926. * register B channel 4 (read/write).
  1927. * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
  1928. * register B channel 4 (read/write).
  1929. *
  1930. * DDAR5 Direct Memory Access (DMA) Device Address Register
  1931. * channel 5 (read/write).
  1932. * DCSR5 Direct Memory Access (DMA) Control and Status
  1933. * Register channel 5 (read/write).
  1934. * DBSA5 Direct Memory Access (DMA) Buffer Start address
  1935. * register A channel 5 (read/write).
  1936. * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
  1937. * register A channel 5 (read/write).
  1938. * DBSB5 Direct Memory Access (DMA) Buffer Start address
  1939. * register B channel 5 (read/write).
  1940. * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
  1941. * register B channel 5 (read/write).
  1942. */
  1943. #define DMASp 0x00000020 /* DMA control reg. Space [byte] */
  1944. #define _DDAR(Nb) /* DMA Device Address Reg. */ \
  1945. /* channel [0..5] */ \
  1946. (0xB0000000 + (Nb)*DMASp)
  1947. #define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \
  1948. /* channel [0..5] (write) */ \
  1949. (0xB0000004 + (Nb)*DMASp)
  1950. #define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \
  1951. /* channel [0..5] (write) */ \
  1952. (0xB0000008 + (Nb)*DMASp)
  1953. #define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \
  1954. /* channel [0..5] (read) */ \
  1955. (0xB000000C + (Nb)*DMASp)
  1956. #define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \
  1957. /* channel [0..5] */ \
  1958. (0xB0000010 + (Nb)*DMASp)
  1959. #define _DBTA(Nb) /* DMA Buffer Transfer count */ \
  1960. /* reg. A channel [0..5] */ \
  1961. (0xB0000014 + (Nb)*DMASp)
  1962. #define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \
  1963. /* channel [0..5] */ \
  1964. (0xB0000018 + (Nb)*DMASp)
  1965. #define _DBTB(Nb) /* DMA Buffer Transfer count */ \
  1966. /* reg. B channel [0..5] */ \
  1967. (0xB000001C + (Nb)*DMASp)
  1968. #define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */
  1969. /* channel 0 */
  1970. #define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */
  1971. /* channel 0 (write) */
  1972. #define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */
  1973. /* channel 0 (write) */
  1974. #define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */
  1975. /* channel 0 (read) */
  1976. #define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */
  1977. /* channel 0 */
  1978. #define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */
  1979. /* reg. A channel 0 */
  1980. #define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */
  1981. /* channel 0 */
  1982. #define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */
  1983. /* reg. B channel 0 */
  1984. #define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
  1985. /* channel 1 */
  1986. #define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */
  1987. /* channel 1 (write) */
  1988. #define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */
  1989. /* channel 1 (write) */
  1990. #define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */
  1991. /* channel 1 (read) */
  1992. #define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
  1993. /* channel 1 */
  1994. #define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */
  1995. /* reg. A channel 1 */
  1996. #define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
  1997. /* channel 1 */
  1998. #define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */
  1999. /* reg. B channel 1 */
  2000. #define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */
  2001. /* channel 2 */
  2002. #define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */
  2003. /* channel 2 (write) */
  2004. #define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */
  2005. /* channel 2 (write) */
  2006. #define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */
  2007. /* channel 2 (read) */
  2008. #define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */
  2009. /* channel 2 */
  2010. #define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */
  2011. /* reg. A channel 2 */
  2012. #define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */
  2013. /* channel 2 */
  2014. #define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */
  2015. /* reg. B channel 2 */
  2016. #define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */
  2017. /* channel 3 */
  2018. #define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */
  2019. /* channel 3 (write) */
  2020. #define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */
  2021. /* channel 3 (write) */
  2022. #define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */
  2023. /* channel 3 (read) */
  2024. #define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */
  2025. /* channel 3 */
  2026. #define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */
  2027. /* reg. A channel 3 */
  2028. #define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */
  2029. /* channel 3 */
  2030. #define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */
  2031. /* reg. B channel 3 */
  2032. #define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */
  2033. /* channel 4 */
  2034. #define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */
  2035. /* channel 4 (write) */
  2036. #define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */
  2037. /* channel 4 (write) */
  2038. #define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */
  2039. /* channel 4 (read) */
  2040. #define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */
  2041. /* channel 4 */
  2042. #define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */
  2043. /* reg. A channel 4 */
  2044. #define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */
  2045. /* channel 4 */
  2046. #define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */
  2047. /* reg. B channel 4 */
  2048. #define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */
  2049. /* channel 5 */
  2050. #define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */
  2051. /* channel 5 (write) */
  2052. #define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */
  2053. /* channel 5 (write) */
  2054. #define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */
  2055. /* channel 5 (read) */
  2056. #define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */
  2057. /* channel 5 */
  2058. #define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */
  2059. /* reg. A channel 5 */
  2060. #define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */
  2061. /* channel 5 */
  2062. #define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */
  2063. /* reg. B channel 5 */
  2064. #if LANGUAGE == C
  2065. #define DDAR0 /* DMA Device Address Reg. */ \
  2066. /* channel 0 */ \
  2067. (*((volatile Word *) io_p2v (_DDAR0)))
  2068. #define SetDCSR0 /* Set DMA Control & Status Reg. */ \
  2069. /* channel 0 (write) */ \
  2070. (*((volatile Word *) io_p2v (_SetDCSR0)))
  2071. #define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
  2072. /* channel 0 (write) */ \
  2073. (*((volatile Word *) io_p2v (_ClrDCSR0)))
  2074. #define RdDCSR0 /* Read DMA Control & Status Reg. */ \
  2075. /* channel 0 (read) */ \
  2076. (*((volatile Word *) io_p2v (_RdDCSR0)))
  2077. #define DBSA0 /* DMA Buffer Start address reg. A */ \
  2078. /* channel 0 */ \
  2079. (*((volatile Address *) io_p2v (_DBSA0)))
  2080. #define DBTA0 /* DMA Buffer Transfer count */ \
  2081. /* reg. A channel 0 */ \
  2082. (*((volatile Word *) io_p2v (_DBTA0)))
  2083. #define DBSB0 /* DMA Buffer Start address reg. B */ \
  2084. /* channel 0 */ \
  2085. (*((volatile Address *) io_p2v (_DBSB0)))
  2086. #define DBTB0 /* DMA Buffer Transfer count */ \
  2087. /* reg. B channel 0 */ \
  2088. (*((volatile Word *) io_p2v (_DBTB0)))
  2089. #define DDAR1 /* DMA Device Address Reg. */ \
  2090. /* channel 1 */ \
  2091. (*((volatile Word *) io_p2v (_DDAR1)))
  2092. #define SetDCSR1 /* Set DMA Control & Status Reg. */ \
  2093. /* channel 1 (write) */ \
  2094. (*((volatile Word *) io_p2v (_SetDCSR1)))
  2095. #define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
  2096. /* channel 1 (write) */ \
  2097. (*((volatile Word *) io_p2v (_ClrDCSR1)))
  2098. #define RdDCSR1 /* Read DMA Control & Status Reg. */ \
  2099. /* channel 1 (read) */ \
  2100. (*((volatile Word *) io_p2v (_RdDCSR1)))
  2101. #define DBSA1 /* DMA Buffer Start address reg. A */ \
  2102. /* channel 1 */ \
  2103. (*((volatile Address *) io_p2v (_DBSA1)))
  2104. #define DBTA1 /* DMA Buffer Transfer count */ \
  2105. /* reg. A channel 1 */ \
  2106. (*((volatile Word *) io_p2v (_DBTA1)))
  2107. #define DBSB1 /* DMA Buffer Start address reg. B */ \
  2108. /* channel 1 */ \
  2109. (*((volatile Address *) io_p2v (_DBSB1)))
  2110. #define DBTB1 /* DMA Buffer Transfer count */ \
  2111. /* reg. B channel 1 */ \
  2112. (*((volatile Word *) io_p2v (_DBTB1)))
  2113. #define DDAR2 /* DMA Device Address Reg. */ \
  2114. /* channel 2 */ \
  2115. (*((volatile Word *) io_p2v (_DDAR2)))
  2116. #define SetDCSR2 /* Set DMA Control & Status Reg. */ \
  2117. /* channel 2 (write) */ \
  2118. (*((volatile Word *) io_p2v (_SetDCSR2)))
  2119. #define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
  2120. /* channel 2 (write) */ \
  2121. (*((volatile Word *) io_p2v (_ClrDCSR2)))
  2122. #define RdDCSR2 /* Read DMA Control & Status Reg. */ \
  2123. /* channel 2 (read) */ \
  2124. (*((volatile Word *) io_p2v (_RdDCSR2)))
  2125. #define DBSA2 /* DMA Buffer Start address reg. A */ \
  2126. /* channel 2 */ \
  2127. (*((volatile Address *) io_p2v (_DBSA2)))
  2128. #define DBTA2 /* DMA Buffer Transfer count */ \
  2129. /* reg. A channel 2 */ \
  2130. (*((volatile Word *) io_p2v (_DBTA2)))
  2131. #define DBSB2 /* DMA Buffer Start address reg. B */ \
  2132. /* channel 2 */ \
  2133. (*((volatile Address *) io_p2v (_DBSB2)))
  2134. #define DBTB2 /* DMA Buffer Transfer count */ \
  2135. /* reg. B channel 2 */ \
  2136. (*((volatile Word *) io_p2v (_DBTB2)))
  2137. #define DDAR3 /* DMA Device Address Reg. */ \
  2138. /* channel 3 */ \
  2139. (*((volatile Word *) io_p2v (_DDAR3)))
  2140. #define SetDCSR3 /* Set DMA Control & Status Reg. */ \
  2141. /* channel 3 (write) */ \
  2142. (*((volatile Word *) io_p2v (_SetDCSR3)))
  2143. #define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
  2144. /* channel 3 (write) */ \
  2145. (*((volatile Word *) io_p2v (_ClrDCSR3)))
  2146. #define RdDCSR3 /* Read DMA Control & Status Reg. */ \
  2147. /* channel 3 (read) */ \
  2148. (*((volatile Word *) io_p2v (_RdDCSR3)))
  2149. #define DBSA3 /* DMA Buffer Start address reg. A */ \
  2150. /* channel 3 */ \
  2151. (*((volatile Address *) io_p2v (_DBSA3)))
  2152. #define DBTA3 /* DMA Buffer Transfer count */ \
  2153. /* reg. A channel 3 */ \
  2154. (*((volatile Word *) io_p2v (_DBTA3)))
  2155. #define DBSB3 /* DMA Buffer Start address reg. B */ \
  2156. /* channel 3 */ \
  2157. (*((volatile Address *) io_p2v (_DBSB3)))
  2158. #define DBTB3 /* DMA Buffer Transfer count */ \
  2159. /* reg. B channel 3 */ \
  2160. (*((volatile Word *) io_p2v (_DBTB3)))
  2161. #define DDAR4 /* DMA Device Address Reg. */ \
  2162. /* channel 4 */ \
  2163. (*((volatile Word *) io_p2v (_DDAR4)))
  2164. #define SetDCSR4 /* Set DMA Control & Status Reg. */ \
  2165. /* channel 4 (write) */ \
  2166. (*((volatile Word *) io_p2v (_SetDCSR4)))
  2167. #define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
  2168. /* channel 4 (write) */ \
  2169. (*((volatile Word *) io_p2v (_ClrDCSR4)))
  2170. #define RdDCSR4 /* Read DMA Control & Status Reg. */ \
  2171. /* channel 4 (read) */ \
  2172. (*((volatile Word *) io_p2v (_RdDCSR4)))
  2173. #define DBSA4 /* DMA Buffer Start address reg. A */ \
  2174. /* channel 4 */ \
  2175. (*((volatile Address *) io_p2v (_DBSA4)))
  2176. #define DBTA4 /* DMA Buffer Transfer count */ \
  2177. /* reg. A channel 4 */ \
  2178. (*((volatile Word *) io_p2v (_DBTA4)))
  2179. #define DBSB4 /* DMA Buffer Start address reg. B */ \
  2180. /* channel 4 */ \
  2181. (*((volatile Address *) io_p2v (_DBSB4)))
  2182. #define DBTB4 /* DMA Buffer Transfer count */ \
  2183. /* reg. B channel 4 */ \
  2184. (*((volatile Word *) io_p2v (_DBTB4)))
  2185. #define DDAR5 /* DMA Device Address Reg. */ \
  2186. /* channel 5 */ \
  2187. (*((volatile Word *) io_p2v (_DDAR5)))
  2188. #define SetDCSR5 /* Set DMA Control & Status Reg. */ \
  2189. /* channel 5 (write) */ \
  2190. (*((volatile Word *) io_p2v (_SetDCSR5)))
  2191. #define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
  2192. /* channel 5 (write) */ \
  2193. (*((volatile Word *) io_p2v (_ClrDCSR5)))
  2194. #define RdDCSR5 /* Read DMA Control & Status Reg. */ \
  2195. /* channel 5 (read) */ \
  2196. (*((volatile Word *) io_p2v (_RdDCSR5)))
  2197. #define DBSA5 /* DMA Buffer Start address reg. A */ \
  2198. /* channel 5 */ \
  2199. (*((volatile Address *) io_p2v (_DBSA5)))
  2200. #define DBTA5 /* DMA Buffer Transfer count */ \
  2201. /* reg. A channel 5 */ \
  2202. (*((volatile Word *) io_p2v (_DBTA5)))
  2203. #define DBSB5 /* DMA Buffer Start address reg. B */ \
  2204. /* channel 5 */ \
  2205. (*((volatile Address *) io_p2v (_DBSB5)))
  2206. #define DBTB5 /* DMA Buffer Transfer count */ \
  2207. /* reg. B channel 5 */ \
  2208. (*((volatile Word *) io_p2v (_DBTB5)))
  2209. #endif /* LANGUAGE == C */
  2210. #define DDAR_RW 0x00000001 /* device data Read/Write */
  2211. #define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
  2212. /* (memory -> device) */
  2213. #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
  2214. /* (device -> memory) */
  2215. #define DDAR_E 0x00000002 /* big/little Endian device */
  2216. #define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
  2217. #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
  2218. #define DDAR_BS 0x00000004 /* device Burst Size */
  2219. #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
  2220. #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
  2221. #define DDAR_DW 0x00000008 /* device Data Width */
  2222. #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
  2223. #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
  2224. #define DDAR_DS Fld (4, 4) /* Device Select */
  2225. #define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
  2226. (0x0 << FShft (DDAR_DS))
  2227. #define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
  2228. (0x1 << FShft (DDAR_DS))
  2229. #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
  2230. (0x2 << FShft (DDAR_DS))
  2231. #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
  2232. (0x3 << FShft (DDAR_DS))
  2233. #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
  2234. (0x4 << FShft (DDAR_DS))
  2235. #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
  2236. (0x5 << FShft (DDAR_DS))
  2237. #define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
  2238. (0x6 << FShft (DDAR_DS))
  2239. #define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
  2240. (0x7 << FShft (DDAR_DS))
  2241. #define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
  2242. (0x8 << FShft (DDAR_DS))
  2243. #define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
  2244. (0x9 << FShft (DDAR_DS))
  2245. #define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
  2246. /* (audio) */ \
  2247. (0xA << FShft (DDAR_DS))
  2248. #define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
  2249. /* (audio) */ \
  2250. (0xB << FShft (DDAR_DS))
  2251. #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
  2252. /* (telecom) */ \
  2253. (0xC << FShft (DDAR_DS))
  2254. #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
  2255. /* (telecom) */ \
  2256. (0xD << FShft (DDAR_DS))
  2257. #define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
  2258. (0xE << FShft (DDAR_DS))
  2259. #define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
  2260. (0xF << FShft (DDAR_DS))
  2261. #define DDAR_DA Fld (24, 8) /* Device Address */
  2262. #define DDAR_DevAdd(Add) /* Device Address */ \
  2263. (((Add) & 0xF0000000) | \
  2264. (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
  2265. #define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
  2266. (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
  2267. DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
  2268. #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
  2269. (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
  2270. DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
  2271. #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
  2272. (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
  2273. DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
  2274. #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
  2275. (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
  2276. DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
  2277. #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
  2278. (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
  2279. DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
  2280. #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
  2281. (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
  2282. DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
  2283. #define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
  2284. (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
  2285. DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
  2286. #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
  2287. (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
  2288. DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
  2289. #define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
  2290. (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
  2291. DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
  2292. #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
  2293. (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
  2294. DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
  2295. #define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
  2296. (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
  2297. DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
  2298. #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
  2299. (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
  2300. DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
  2301. #define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
  2302. (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
  2303. DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
  2304. #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
  2305. (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
  2306. DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
  2307. #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
  2308. /* (telecom) */ \
  2309. (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
  2310. DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
  2311. #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
  2312. /* (telecom) */ \
  2313. (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
  2314. DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
  2315. #define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
  2316. (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
  2317. DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
  2318. #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
  2319. (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
  2320. DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
  2321. #define DCSR_RUN 0x00000001 /* DMA RUNing */
  2322. #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
  2323. #define DCSR_ERROR 0x00000004 /* DMA ERROR */
  2324. #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
  2325. #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
  2326. #define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
  2327. #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
  2328. #define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
  2329. #define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
  2330. #define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
  2331. #define DBT_TC Fld (13, 0) /* Transfer Count */
  2332. #define DBTA_TCA DBT_TC /* Transfer Count buffer A */
  2333. #define DBTB_TCB DBT_TC /* Transfer Count buffer B */
  2334. /*
  2335. * Liquid Crystal Display (LCD) control registers
  2336. *
  2337. * Registers
  2338. * LCCR0 Liquid Crystal Display (LCD) Control Register 0
  2339. * (read/write).
  2340. * [Bits LDM, BAM, and ERM are only implemented in
  2341. * versions 2.0 (rev. = 8) and higher of the StrongARM
  2342. * SA-1100.]
  2343. * LCSR Liquid Crystal Display (LCD) Status Register
  2344. * (read/write).
  2345. * [Bit LDD can be only read in versions 1.0 (rev. = 1)
  2346. * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
  2347. * read and written (cleared) in versions 2.0 (rev. = 8)
  2348. * and higher.]
  2349. * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
  2350. * (DMA) Base Address Register channel 1 (read/write).
  2351. * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
  2352. * (DMA) Current Address Register channel 1 (read).
  2353. * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
  2354. * (DMA) Base Address Register channel 2 (read/write).
  2355. * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
  2356. * (DMA) Current Address Register channel 2 (read).
  2357. * LCCR1 Liquid Crystal Display (LCD) Control Register 1
  2358. * (read/write).
  2359. * [The LCCR1 register can be only written in
  2360. * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
  2361. * StrongARM SA-1100, it can be written and read in
  2362. * versions 2.0 (rev. = 8) and higher.]
  2363. * LCCR2 Liquid Crystal Display (LCD) Control Register 2
  2364. * (read/write).
  2365. * [The LCCR1 register can be only written in
  2366. * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
  2367. * StrongARM SA-1100, it can be written and read in
  2368. * versions 2.0 (rev. = 8) and higher.]
  2369. * LCCR3 Liquid Crystal Display (LCD) Control Register 3
  2370. * (read/write).
  2371. * [The LCCR1 register can be only written in
  2372. * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
  2373. * StrongARM SA-1100, it can be written and read in
  2374. * versions 2.0 (rev. = 8) and higher. Bit PCP is only
  2375. * implemented in versions 2.0 (rev. = 8) and higher of
  2376. * the StrongARM SA-1100.]
  2377. *
  2378. * Clocks
  2379. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  2380. * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
  2381. * fpix, Tpix Frequency, period of the pixel clock.
  2382. * fln, Tln Frequency, period of the line clock.
  2383. * fac, Tac Frequency, period of the AC bias clock.
  2384. */
  2385. #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
  2386. #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
  2387. /* [byte] */ \
  2388. (16*LCD_PEntrySp)
  2389. #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
  2390. /* [byte] */ \
  2391. (256*LCD_PEntrySp)
  2392. #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
  2393. /* dummy-Palette Space [byte] */ \
  2394. (16*LCD_PEntrySp)
  2395. #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
  2396. #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
  2397. #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
  2398. #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
  2399. #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
  2400. #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
  2401. (0 << FShft (LCD_PBS))
  2402. #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
  2403. (1 << FShft (LCD_PBS))
  2404. #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
  2405. (2 << FShft (LCD_PBS))
  2406. #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
  2407. #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
  2408. #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
  2409. #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
  2410. #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
  2411. #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
  2412. #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
  2413. #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
  2414. #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
  2415. #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
  2416. #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
  2417. #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
  2418. #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
  2419. #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
  2420. #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
  2421. #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
  2422. /* (Alternative) */
  2423. #define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */
  2424. #define _LCSR 0xB0100004 /* LCD Status Reg. */
  2425. #define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
  2426. /* channel 1 */
  2427. #define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
  2428. /* channel 1 */
  2429. #define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
  2430. /* channel 2 */
  2431. #define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
  2432. /* channel 2 */
  2433. #define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
  2434. #define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */
  2435. #define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */
  2436. #if LANGUAGE == C
  2437. #define LCCR0 /* LCD Control Reg. 0 */ \
  2438. (*((volatile Word *) io_p2v (_LCCR0)))
  2439. #define LCSR /* LCD Status Reg. */ \
  2440. (*((volatile Word *) io_p2v (_LCSR)))
  2441. #define DBAR1 /* LCD DMA Base Address Reg. */ \
  2442. /* channel 1 */ \
  2443. (*((volatile Address *) io_p2v (_DBAR1)))
  2444. #define DCAR1 /* LCD DMA Current Address Reg. */ \
  2445. /* channel 1 */ \
  2446. (*((volatile Address *) io_p2v (_DCAR1)))
  2447. #define DBAR2 /* LCD DMA Base Address Reg. */ \
  2448. /* channel 2 */ \
  2449. (*((volatile Address *) io_p2v (_DBAR2)))
  2450. #define DCAR2 /* LCD DMA Current Address Reg. */ \
  2451. /* channel 2 */ \
  2452. (*((volatile Address *) io_p2v (_DCAR2)))
  2453. #define LCCR1 /* LCD Control Reg. 1 */ \
  2454. (*((volatile Word *) io_p2v (_LCCR1)))
  2455. #define LCCR2 /* LCD Control Reg. 2 */ \
  2456. (*((volatile Word *) io_p2v (_LCCR2)))
  2457. #define LCCR3 /* LCD Control Reg. 3 */ \
  2458. (*((volatile Word *) io_p2v (_LCCR3)))
  2459. #endif /* LANGUAGE == C */
  2460. #define LCCR0_LEN 0x00000001 /* LCD ENable */
  2461. #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
  2462. #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
  2463. #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
  2464. #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
  2465. /* Select */
  2466. #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
  2467. #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
  2468. #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
  2469. /* interrupt Mask (disable) */
  2470. #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
  2471. /* interrupt Mask (disable) */
  2472. #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
  2473. /* IUU, OOL, OUL, OOU, and OUU) */
  2474. /* interrupt Mask (disable) */
  2475. #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
  2476. #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
  2477. #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
  2478. #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
  2479. #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
  2480. #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
  2481. #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
  2482. /* display mode) */
  2483. #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
  2484. /* display */
  2485. #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
  2486. /* display */
  2487. #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
  2488. /* [Tmem] */
  2489. #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
  2490. /* [0..510 Tcpu] */ \
  2491. ((Tcpu)/2 << FShft (LCCR0_PDD))
  2492. #define LCSR_LDD 0x00000001 /* LCD Disable Done */
  2493. #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
  2494. #define LCSR_BER 0x00000004 /* Bus ERror */
  2495. #define LCSR_ABC 0x00000008 /* AC Bias clock Count */
  2496. #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
  2497. /* panel */
  2498. #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
  2499. /* panel */
  2500. #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
  2501. /* panel */
  2502. #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
  2503. /* panel */
  2504. #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
  2505. /* panel */
  2506. #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
  2507. /* panel */
  2508. #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
  2509. /* panel */
  2510. #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
  2511. /* panel */
  2512. #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
  2513. #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
  2514. (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
  2515. #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
  2516. /* pulse Width - 2 [Tpix] (L_LCLK) */
  2517. #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
  2518. /* pulse Width [2..65 Tpix] */ \
  2519. (((Tpix) - 2) << FShft (LCCR1_HSW))
  2520. #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
  2521. /* count - 1 [Tpix] */
  2522. #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
  2523. /* [1..256 Tpix] */ \
  2524. (((Tpix) - 1) << FShft (LCCR1_ELW))
  2525. #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
  2526. /* Wait count - 1 [Tpix] */
  2527. #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
  2528. /* [1..256 Tpix] */ \
  2529. (((Tpix) - 1) << FShft (LCCR1_BLW))
  2530. #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
  2531. #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
  2532. (((Line) - 1) << FShft (LCCR2_LPP))
  2533. #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
  2534. /* Width - 1 [Tln] (L_FCLK) */
  2535. #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
  2536. /* Width [1..64 Tln] */ \
  2537. (((Tln) - 1) << FShft (LCCR2_VSW))
  2538. #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
  2539. /* count [Tln] */
  2540. #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
  2541. /* [0..255 Tln] */ \
  2542. ((Tln) << FShft (LCCR2_EFW))
  2543. #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
  2544. /* Wait count [Tln] */
  2545. #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
  2546. /* [0..255 Tln] */ \
  2547. ((Tln) << FShft (LCCR2_BFW))
  2548. #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
  2549. /* [1..255] (L_PCLK) */
  2550. /* fpix = fcpu/(2*(PCD + 2)) */
  2551. /* Tpix = 2*(PCD + 2)*Tcpu */
  2552. #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
  2553. (((Div) - 4)/2 << FShft (LCCR3_PCD))
  2554. /* fpix = fcpu/(2*Floor (Div/2)) */
  2555. /* Tpix = 2*Floor (Div/2)*Tcpu */
  2556. #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
  2557. (((Div) - 3)/2 << FShft (LCCR3_PCD))
  2558. /* fpix = fcpu/(2*Ceil (Div/2)) */
  2559. /* Tpix = 2*Ceil (Div/2)*Tcpu */
  2560. #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
  2561. /* [Tln] (L_BIAS) */
  2562. #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
  2563. (((Div) - 2)/2 << FShft (LCCR3_ACB))
  2564. /* fac = fln/(2*Floor (Div/2)) */
  2565. /* Tac = 2*Floor (Div/2)*Tln */
  2566. #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
  2567. (((Div) - 1)/2 << FShft (LCCR3_ACB))
  2568. /* fac = fln/(2*Ceil (Div/2)) */
  2569. /* Tac = 2*Ceil (Div/2)*Tln */
  2570. #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
  2571. /* Interrupt */
  2572. #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
  2573. /* Off */ \
  2574. (0 << FShft (LCCR3_API))
  2575. #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
  2576. /* [1..15] */ \
  2577. ((Trans) << FShft (LCCR3_API))
  2578. #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
  2579. /* Polarity (L_FCLK) */
  2580. #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
  2581. /* active High */
  2582. #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
  2583. /* active Low */
  2584. #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
  2585. /* pulse Polarity (L_LCLK) */
  2586. #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
  2587. /* pulse active High */
  2588. #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
  2589. /* pulse active Low */
  2590. #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
  2591. #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
  2592. #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
  2593. #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
  2594. /* active display mode) */
  2595. #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
  2596. #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
  2597. #undef C
  2598. #undef Assembly