imx6.txt 4.6 KB

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  1. U-Boot for Freescale i.MX6
  2. This file contains information for the port of U-Boot to the Freescale i.MX6
  3. SoC.
  4. 1. CONVENTIONS FOR FUSE ASSIGNMENTS
  5. -----------------------------------
  6. 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
  7. 16 msbs in word 3[15:0].
  8. For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address
  9. is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in
  10. word 4.
  11. Example:
  12. For reading the MAC address fuses on a MX6Q:
  13. - The MAC address is stored in two fuse addresses (the fuse addresses are
  14. described in the Fusemap Descriptions table from the mx6q Reference Manual):
  15. 0x620[31:0] - MAC_ADDR[31:0]
  16. 0x630[15:0] - MAC_ADDR[47:32]
  17. In order to use the fuse API, we need to pass the bank and word values, which
  18. are calculated as below:
  19. Fuse address for the lower MAC address: 0x620
  20. Base address for the fuses: 0x400
  21. (0x620 - 0x400)/0x10 = 0x22 = 34 decimal
  22. As the fuses are arranged in banks of 8 words:
  23. 34 / 8 = 4 and the remainder is 2, so in this case:
  24. bank = 4
  25. word = 2
  26. And the U-Boot command would be:
  27. => fuse read 4 2
  28. Reading bank 4:
  29. Word 0x00000002: 9f027772
  30. Doing the same for the upper MAC address:
  31. Fuse address for the upper MAC address: 0x630
  32. Base address for the fuses: 0x400
  33. (0x630 - 0x400)/0x10 = 0x23 = 35 decimal
  34. As the fuses are arranged in banks of 8 words:
  35. 35 / 8 = 4 and the remainder is 3, so in this case:
  36. bank = 4
  37. word = 3
  38. And the U-Boot command would be:
  39. => fuse read 4 3
  40. Reading bank 4:
  41. Word 0x00000003: 00000004
  42. ,which matches the ethaddr value:
  43. => echo ${ethaddr}
  44. 00:04:9f:02:77:72
  45. Some other useful hints:
  46. - The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference
  47. Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register
  48. Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual,
  49. Rev. 1, 04/2013" document. For example, for the MAC fuses we have:
  50. Address:
  51. 21B_C620 Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0)
  52. 21B_C630 Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1)
  53. - The command '=> fuse read 4 2 2' reads the whole MAC addresses at once:
  54. => fuse read 4 2 2
  55. Reading bank 4:
  56. Word 0x00000002: 9f027772 00000004
  57. NAND Boot on i.MX6 with SPL support
  58. --------------------------------------
  59. Writing/updating boot image in nand device is not straight forward in
  60. i.MX6 platform and it requires boot control block(BCB) to be configured.
  61. BCB contains two data structures, Firmware Configuration Block(FCB) and
  62. Discovered Bad Block Table(DBBT). FCB has nand timings, DBBT search area,
  63. and firmware. See IMX6DQRM Section 8.5.2.2
  64. for more information.
  65. We can't use 'nand write' command to write SPL/firmware image directly
  66. like other platforms does. So we need special setup to write BCB block
  67. as per IMX6QDL reference manual 'nandbcb update' command do that job.
  68. for nand boot, up on reset bootrom look for FCB structure in
  69. first block's if FCB found the nand timings are loaded for
  70. further reads. once FCB read done, DTTB will be loaded and
  71. finally firmware will be loaded which is boot image.
  72. cmd_nandbcb will create FCB these structures
  73. by taking mtd partition as an example.
  74. - initial code will erase entire partition
  75. - followed by FCB setup, like first 2 blocks for FCB/DBBT write,
  76. and next block for FW1/SPL
  77. - write firmware at FW1 block and
  78. - finally write fcb/dttb in first 2 block.
  79. Typical NAND BCB layout:
  80. =======================
  81. no.of blocks = partition size / erasesize
  82. no.of fcb/dbbt blocks = 2
  83. FW1 offset = no.of fcb/dbbt
  84. block 0 1 2
  85. -------------------------------
  86. |FCB/DBBT 0|FCB/DBBT 1| FW 1 |
  87. --------------------------------
  88. On summary, nandbcb update will
  89. - erase the entire partition
  90. - create BCB by creating 2 FCB/BDDT block followed by
  91. 1 FW blocks based on partition size and erasesize.
  92. - fill FCB/DBBT structures
  93. - write FW/SPL in FW1
  94. - write FCB/DBBT in first 2 blocks
  95. step-1: write SPL
  96. icorem6qdl> ext4load mmc 0:1 $loadaddr SPL
  97. 39936 bytes read in 10 ms (3.8 MiB/s)
  98. icorem6qdl> nandbcb update $loadaddr spl $filesize
  99. device 0 offset 0x0, size 0x9c00
  100. Erasing at 0x1c0000 -- 100% complete.
  101. NAND fw write: 0x80000 offset, 0xb000 bytes written: OK
  102. step-2: write u-boot-dtb.img
  103. icorem6qdl> nand erase.part uboot
  104. NAND erase.part: device 0 offset 0x200000, size 0x200000
  105. Erasing at 0x3c0000 -- 100% complete.
  106. OK
  107. icorem6qdl> ext4load mmc 0:1 $loadaddr u-boot-dtb.img
  108. 589094 bytes read in 37 ms (15.2 MiB/s)
  109. icorem6qdl> nand write ${loadaddr} uboot ${filesize}
  110. NAND write: device 0 offset 0x200000, size 0x8fd26
  111. 589094 bytes written: OK
  112. icorem6qdl>