spi-stm32-qspi.txt 1.3 KB

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  1. * STMicroelectronics Quad Serial Peripheral Interface(QSPI)
  2. Required properties:
  3. - compatible: should be "st,stm32f469-qspi"
  4. - reg: the first contains the register location and length.
  5. the second contains the memory mapping address and length
  6. - reg-names: should contain the reg names "qspi" "qspi_mm"
  7. - interrupts: should contain the interrupt for the device
  8. - clocks: the phandle of the clock needed by the QSPI controller
  9. - A pinctrl must be defined to set pins in mode of operation for QSPI transfer
  10. Optional properties:
  11. - resets: must contain the phandle to the reset controller.
  12. A spi flash (NOR/NAND) must be a child of spi node and could have some
  13. properties. Also see jedec,spi-nor.txt.
  14. Required properties:
  15. - reg: chip-Select number (QSPI controller may connect 2 flashes)
  16. - spi-max-frequency: max frequency of spi bus
  17. Optional property:
  18. - spi-rx-bus-width: see ./spi-bus.txt for the description
  19. Example:
  20. qspi: spi@a0001000 {
  21. compatible = "st,stm32f469-qspi";
  22. reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
  23. reg-names = "qspi", "qspi_mm";
  24. interrupts = <91>;
  25. resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
  26. clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
  27. pinctrl-names = "default";
  28. pinctrl-0 = <&pinctrl_qspi0>;
  29. flash@0 {
  30. compatible = "jedec,spi-nor";
  31. reg = <0>;
  32. spi-rx-bus-width = <4>;
  33. spi-max-frequency = <108000000>;
  34. ...
  35. };
  36. };