st,stm32-pinctrl.txt 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208
  1. * STM32 GPIO and Pin Mux/Config controller
  2. STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
  3. controller. It controls the input/output settings on the available pins and
  4. also provides ability to multiplex and configure the output of various on-chip
  5. controllers onto these pads.
  6. Pin controller node:
  7. Required properies:
  8. - compatible: value should be one of the following:
  9. "st,stm32f429-pinctrl"
  10. "st,stm32f469-pinctrl"
  11. "st,stm32f746-pinctrl"
  12. "st,stm32f769-pinctrl"
  13. "st,stm32h743-pinctrl"
  14. "st,stm32mp157-pinctrl"
  15. "st,stm32mp157-z-pinctrl"
  16. - #address-cells: The value of this property must be 1
  17. - #size-cells : The value of this property must be 1
  18. - ranges : defines mapping between pin controller node (parent) to
  19. gpio-bank node (children).
  20. - pins-are-numbered: Specify the subnodes are using numbered pinmux to
  21. specify pins.
  22. GPIO controller/bank node:
  23. Required properties:
  24. - gpio-controller : Indicates this device is a GPIO controller
  25. - #gpio-cells : Should be two.
  26. The first cell is the pin number
  27. The second one is the polarity:
  28. - 0 for active high
  29. - 1 for active low
  30. - reg : The gpio address range, relative to the pinctrl range
  31. - clocks : clock that drives this bank
  32. - st,bank-name : Should be a name string for this bank as specified in
  33. the datasheet
  34. Optional properties:
  35. - reset: : Reference to the reset controller
  36. - st,syscfg: Should be phandle/offset/mask.
  37. -The phandle to the syscon node which includes IRQ mux selection register.
  38. -The offset of the IRQ mux selection register
  39. -The field mask of IRQ mux, needed if different of 0xf.
  40. - gpio-ranges: Define a dedicated mapping between a pin-controller and
  41. a gpio controller. Format is <&phandle a b c> with:
  42. -(phandle): phandle of pin-controller.
  43. -(a): gpio base offset in range.
  44. -(b): pin base offset in range.
  45. -(c): gpio count in range
  46. This entry has to be used either if there are holes inside a bank:
  47. GPIOB0/B1/B2/B14/B15 (see example 2)
  48. or if banks are not contiguous:
  49. GPIOA/B/C/E...
  50. NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
  51. have to use a "gpio-ranges" entry.
  52. More details in Documentation/devicetree/bindings/gpio/gpio.txt.
  53. - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
  54. used to select GPIOs as interrupts).
  55. - hwlocks: reference to a phandle of a hardware spinlock provider node.
  56. - st,package: Indicates the SOC package used.
  57. More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
  58. Example 1:
  59. #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
  60. ...
  61. pin-controller {
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. compatible = "st,stm32f429-pinctrl";
  65. ranges = <0 0x40020000 0x3000>;
  66. pins-are-numbered;
  67. gpioa: gpio@40020000 {
  68. gpio-controller;
  69. #gpio-cells = <2>;
  70. reg = <0x0 0x400>;
  71. resets = <&reset_ahb1 0>;
  72. st,bank-name = "GPIOA";
  73. };
  74. ...
  75. pin-functions nodes follow...
  76. };
  77. Example 2:
  78. #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
  79. ...
  80. pinctrl: pin-controller {
  81. #address-cells = <1>;
  82. #size-cells = <1>;
  83. compatible = "st,stm32f429-pinctrl";
  84. ranges = <0 0x40020000 0x3000>;
  85. pins-are-numbered;
  86. gpioa: gpio@40020000 {
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. reg = <0x0 0x400>;
  90. resets = <&reset_ahb1 0>;
  91. st,bank-name = "GPIOA";
  92. gpio-ranges = <&pinctrl 0 0 16>;
  93. };
  94. gpiob: gpio@40020400 {
  95. gpio-controller;
  96. #gpio-cells = <2>;
  97. reg = <0x0 0x400>;
  98. resets = <&reset_ahb1 0>;
  99. st,bank-name = "GPIOB";
  100. ngpios = 4;
  101. gpio-ranges = <&pinctrl 0 16 3>,
  102. <&pinctrl 14 30 2>;
  103. };
  104. ...
  105. pin-functions nodes follow...
  106. };
  107. Contents of function subnode node:
  108. ----------------------------------
  109. Subnode format
  110. A pinctrl node should contain at least one subnode representing the
  111. pinctrl group available on the machine. Each subnode will list the
  112. pins it needs, and how they should be configured, with regard to muxer
  113. configuration, pullups, drive, output high/low and output speed.
  114. node {
  115. pinmux = <PIN_NUMBER_PINMUX>;
  116. GENERIC_PINCONFIG;
  117. };
  118. Required properties:
  119. - pinmux: integer array, represents gpio pin number and mux setting.
  120. Supported pin number and mux varies for different SoCs, and are defined in
  121. dt-bindings/pinctrl/<soc>-pinfunc.h directly.
  122. These defines are calculated as:
  123. ((port * 16 + line) << 8) | function
  124. With:
  125. - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
  126. - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
  127. - function: The function number, can be:
  128. * 0 : GPIO
  129. * 1 : Alternate Function 0
  130. * 2 : Alternate Function 1
  131. * 3 : Alternate Function 2
  132. * ...
  133. * 16 : Alternate Function 15
  134. * 17 : Analog
  135. To simplify the usage, macro is available to generate "pinmux" field.
  136. This macro is available here:
  137. - include/dt-bindings/pinctrl/stm32-pinfunc.h
  138. Some examples of using macro:
  139. /* GPIO A9 set as alernate function 2 */
  140. ... {
  141. pinmux = <STM32_PINMUX('A', 9, AF2)>;
  142. };
  143. /* GPIO A9 set as GPIO */
  144. ... {
  145. pinmux = <STM32_PINMUX('A', 9, GPIO)>;
  146. };
  147. /* GPIO A9 set as analog */
  148. ... {
  149. pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
  150. };
  151. Optional properties:
  152. - GENERIC_PINCONFIG: is the generic pinconfig options to use.
  153. Available options are:
  154. - bias-disable,
  155. - bias-pull-down,
  156. - bias-pull-up,
  157. - drive-push-pull,
  158. - drive-open-drain,
  159. - output-low
  160. - output-high
  161. - slew-rate = <x>, with x being:
  162. < 0 > : Low speed
  163. < 1 > : Medium speed
  164. < 2 > : Fast speed
  165. < 3 > : High speed
  166. Example:
  167. pin-controller {
  168. ...
  169. usart1_pins_a: usart1@0 {
  170. pins1 {
  171. pinmux = <STM32_PINMUX('A', 9, AF7)>;
  172. bias-disable;
  173. drive-push-pull;
  174. slew-rate = <0>;
  175. };
  176. pins2 {
  177. pinmux = <STM32_PINMUX('A', 10, AF7)>;
  178. bias-disable;
  179. };
  180. };
  181. };
  182. &usart1 {
  183. pinctrl-0 = <&usart1_pins_a>;
  184. pinctrl-names = "default";
  185. };