ti,dp83867.txt 1.4 KB

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  1. * Texas Instruments - dp83867 Giga bit ethernet phy
  2. Required properties:
  3. - reg - The ID number for the phy, usually a small integer
  4. - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
  5. for applicable values
  6. - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
  7. for applicable values
  8. - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
  9. for applicable values
  10. - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
  11. compensate for the board being designed with the lanes swapped.
  12. - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
  13. TX/RX lanes.
  14. - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
  15. for applicable values. The CLK_OUT pin can also
  16. be disabled by this property. When omitted, the
  17. PHY's default will be left as is.
  18. Default child nodes are standard Ethernet PHY device
  19. nodes as described in doc/devicetree/bindings/net/ethernet.txt
  20. Example:
  21. ethernet-phy@0 {
  22. reg = <0>;
  23. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  24. ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
  25. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  26. enet-phy-lane-no-swap;
  27. ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
  28. };
  29. Datasheet can be found:
  30. http://www.ti.com/product/DP83867IR/datasheet