stm32-fmc2-nand.txt 1.8 KB

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  1. STMicroelectronics Flexible Memory Controller 2 (FMC2)
  2. NAND Interface
  3. Required properties:
  4. - compatible: Should be one of:
  5. * st,stm32mp15-fmc2
  6. - reg: NAND flash controller memory areas.
  7. First region contains the register location.
  8. Regions 2 to 4 respectively contain the data, command,
  9. and address space for CS0.
  10. Regions 5 to 7 contain the same areas for CS1.
  11. - interrupts: The interrupt number
  12. - pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
  13. - clocks: The clock needed by the NAND flash controller
  14. Optional properties:
  15. - resets: Reference to a reset controller asserting the FMC controller
  16. - dmas: DMA specifiers (see: dma/stm32-mdma.txt)
  17. - dma-names: Must be "tx", "rx" and "ecc"
  18. Optional children nodes:
  19. Children nodes represent the available NAND chips.
  20. Optional properties:
  21. - nand-on-flash-bbt: see nand.txt
  22. - nand-ecc-strength: see nand.txt
  23. - nand-ecc-step-size: see nand.txt
  24. The following ECC strength and step size are currently supported:
  25. - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
  26. - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
  27. - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default)
  28. Example:
  29. fmc: nand-controller@58002000 {
  30. compatible = "st,stm32mp15-fmc2";
  31. reg = <0x58002000 0x1000>,
  32. <0x80000000 0x1000>,
  33. <0x88010000 0x1000>,
  34. <0x88020000 0x1000>,
  35. <0x81000000 0x1000>,
  36. <0x89010000 0x1000>,
  37. <0x89020000 0x1000>;
  38. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  39. clocks = <&rcc FMC_K>;
  40. resets = <&rcc FMC_R>;
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&fmc_pins_a>;
  43. #address-cells = <1>;
  44. #size-cells = <0>;
  45. nand@0 {
  46. reg = <0>;
  47. nand-on-flash-bbt;
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. };
  51. };