intel,irq-router.txt 2.8 KB

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  1. Intel Interrupt Router Device Binding
  2. =====================================
  3. The device tree node which describes the operation of the Intel Interrupt Router
  4. device is as follows:
  5. Required properties :
  6. - reg : Specifies the interrupt router's PCI configuration space address as
  7. defined by the Open Firmware spec.
  8. - compatible = "intel,irq-router"
  9. - intel,pirq-config : Specifies the IRQ routing register programming mechanism.
  10. Valid values are:
  11. "pci": IRQ routing is controlled by PCI configuration registers
  12. "ibase": IRQ routing is in the memory-mapped IBASE register block
  13. - intel,ibase-offset : IBASE register offset in the interrupt router's PCI
  14. configuration space, required only if intel,pirq-config = "ibase".
  15. - intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
  16. be specified. The 8-bit ACTL register is seen on ICH series chipset, like
  17. ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
  18. - intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
  19. in the interrupt router's PCI configuration space, or IBASE.
  20. - intel,pirq-link : Specifies the PIRQ link information with two cells. The
  21. first cell is the register offset that controls the first PIRQ link routing.
  22. The second cell is the total number of PIRQ links the router supports.
  23. - intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links,
  24. encoded as 2 cells a group for each link. The first cell is the PIRQ link
  25. number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing
  26. register offset from the interrupt router's base address. If this property
  27. is omitted, it indicates a consecutive register offset from the first PIRQ
  28. link, as specified by the first cell of intel,pirq-link.
  29. - intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
  30. 8259 PIC. Bit N is 1 means IRQ N is available to be routed.
  31. - intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
  32. encoded as 3 cells a group for a device. The first cell is the device's PCI
  33. bus number, device number and function number encoding with PCI_BDF() macro.
  34. The second cell is the PCI interrupt pin used by this device. The last cell
  35. is which PIRQ line the PCI interrupt pin is routed to.
  36. Example
  37. -------
  38. #include <dt-bindings/interrupt-router/intel-irq.h>
  39. irq-router@1f,0 {
  40. reg = <0x0000f800 0 0 0 0>;
  41. compatible = "intel,irq-router";
  42. intel,pirq-config = "pci";
  43. intel,pirq-link = <0x60 8>;
  44. intel,pirq-mask = <0xdef8>;
  45. intel,pirq-routing = <
  46. PCI_BDF(0, 2, 0) INTA PIRQA
  47. PCI_BDF(0, 3, 0) INTA PIRQB
  48. PCI_BDF(0, 8, 0) INTA PIRQC
  49. PCI_BDF(0, 8, 1) INTB PIRQD
  50. PCI_BDF(1, 6, 0) INTA PIRQE
  51. PCI_BDF(1, 6, 1) INTB PIRQF
  52. PCI_BDF(1, 6, 2) INTC PIRQG
  53. PCI_BDF(1, 6, 3) INTD PIRQH
  54. >;
  55. };