st,stm32mp1.txt 8.6 KB

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  1. STMicroelectronics STM32MP1 clock tree initialization
  2. =====================================================
  3. The STM32MP1 clock tree initialization is based on device tree information
  4. for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes.
  5. RCC IP = st,stm32mp1-rcc
  6. ========================
  7. The RCC IP is both a reset and a clock controller but this documentation only
  8. describes the fields added for clock tree initialization which are not present
  9. in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
  10. file.
  11. The added properties for clock tree initialization are:
  12. Required properties:
  13. - st,clksrc : The clock sources configuration array in a platform specific
  14. order.
  15. For the STM32MP15x family there are 9 clock sources selector which are
  16. configured in the following order:
  17. MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
  18. Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE>
  19. from dt-bindings/clock/stm32mp1-clksrc.h.
  20. Example:
  21. st,clksrc = <
  22. CLK_MPU_PLL1P
  23. CLK_AXI_PLL2P
  24. CLK_MCU_PLL3P
  25. CLK_PLL12_HSE
  26. CLK_PLL3_HSE
  27. CLK_PLL4_HSE
  28. CLK_RTC_LSE
  29. CLK_MCO1_DISABLED
  30. CLK_MCO2_DISABLED
  31. >;
  32. - st,clkdiv : The clock main dividers value specified in an array
  33. in a platform specific order.
  34. When used, it shall describe the whole clock dividers tree.
  35. For the STM32MP15x family there are 11 dividers values expected.
  36. They shall be configured in the following order:
  37. MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
  38. The each divider value uses the DIV coding defined in RCC associated
  39. register RCC_xxxDIVR. In most the case, it is:
  40. 0x0: not divided
  41. 0x1: division by 2
  42. 0x2: division by 4
  43. 0x3: division by 8
  44. ...
  45. Note that for RTC MCO1 MCO2, the coding is different:
  46. 0x0: not divided
  47. 0x1: division by 2
  48. 0x2: division by 3
  49. 0x3: division by 4
  50. ...
  51. Example:
  52. st,clkdiv = <
  53. 1 /*MPU*/
  54. 0 /*AXI*/
  55. 0 /*MCU*/
  56. 1 /*APB1*/
  57. 1 /*APB2*/
  58. 1 /*APB3*/
  59. 1 /*APB4*/
  60. 2 /*APB5*/
  61. 23 /*RTC*/
  62. 0 /*MCO1*/
  63. 0 /*MCO2*/
  64. >;
  65. Optional Properties:
  66. - st,pll : A specific PLL configuration, including frequency.
  67. PLL children nodes for PLL1 to PLL4 (see ref manual for details)
  68. are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
  69. PLLx is off when the associated node is absent.
  70. Here are the available properties for each PLL node:
  71. - cfg: The parameters for PLL configuration in the following order:
  72. DIVM DIVN DIVP DIVQ DIVR Output.
  73. DIVx values are defined as in RCC spec:
  74. 0x0: bypass (division by 1)
  75. 0x1: division by 2
  76. 0x2: division by 3
  77. 0x3: division by 4
  78. ...
  79. Output contains a bitfield for each output value (1:ON/0:OFF)
  80. BIT(0) => output P : DIVPEN
  81. BIT(1) => output Q : DIVQEN
  82. BIT(2) => output R : DIVREN
  83. NB: macro PQR(p,q,r) can be used to build this value
  84. with p,q,r = 0 or 1.
  85. - frac : Fractional part of the multiplication factor
  86. (optional, PLL is in integer mode when absent).
  87. - csg : Clock Spreading Generator (optional) with parameters in the
  88. following order: MOD_PER INC_STEP SSCG_MODE.
  89. MOD_PER: Modulation Period Adjustment
  90. INC_STEP: Modulation Depth Adjustment
  91. SSCG_MODE: Spread spectrum clock generator mode, with associated
  92. defined from stm32mp1-clksrc.h:
  93. - SSCG_MODE_CENTER_SPREAD = 0
  94. - SSCG_MODE_DOWN_SPREAD = 1
  95. Example:
  96. st,pll@0 {
  97. cfg = < 1 53 0 0 0 1 >;
  98. frac = < 0x810 >;
  99. };
  100. st,pll@1 {
  101. cfg = < 1 43 1 0 0 PQR(0,1,1) >;
  102. csg = < 10 20 1 >;
  103. };
  104. st,pll@2 {
  105. cfg = < 2 85 3 13 3 0 >;
  106. csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
  107. };
  108. st,pll@3 {
  109. cfg = < 2 78 4 7 9 3 >;
  110. };
  111. - st,pkcs : used to configure the peripherals kernel clock selection.
  112. The property is a list of peripheral kernel clock source identifiers defined
  113. by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file
  114. dt-bindings/clock/stm32mp1-clksrc.h.
  115. st,pkcs may not list all the kernel clocks and has no ordering requirements.
  116. Example:
  117. st,pkcs = <
  118. CLK_STGEN_HSE
  119. CLK_CKPER_HSI
  120. CLK_USBPHY_PLL2P
  121. CLK_DSI_PLL2Q
  122. CLK_I2C46_HSI
  123. CLK_UART1_HSI
  124. CLK_UART24_HSI
  125. >;
  126. other clocks = fixed-clock
  127. ==========================
  128. The clock tree is also based on 5 fixed-clock in clocks node
  129. used to define the state of associated ST32MP1 oscillators:
  130. - clk-lsi
  131. - clk-lse
  132. - clk-hsi
  133. - clk-hse
  134. - clk-csi
  135. At boot the clock tree initialization will
  136. - enable oscillators present in device tree and not disabled
  137. (node with status="disabled"),
  138. - disable HSI oscillator if the node is absent (always activated by bootrom)
  139. and not disabled (node with status="disabled").
  140. Optional properties :
  141. a) for external oscillator: "clk-lse", "clk-hse"
  142. 4 optional fields are managed
  143. - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP)
  144. - "st,digbypass" configures the bypass mode as full-swing digital
  145. signal (DIGBYP)
  146. - "st,css" activates the clock security system (HSECSSON, LSECSSON)
  147. - "st,drive" (only for LSE) contains the value of the drive for the
  148. oscillator (see LSEDRV_ defined in the file
  149. dt-bindings/clock/stm32mp1-clksrc.h)
  150. Example board file:
  151. / {
  152. clocks {
  153. clk_hse: clk-hse {
  154. #clock-cells = <0>;
  155. compatible = "fixed-clock";
  156. clock-frequency = <64000000>;
  157. st,bypass;
  158. };
  159. clk_lse: clk-lse {
  160. #clock-cells = <0>;
  161. compatible = "fixed-clock";
  162. clock-frequency = <32768>;
  163. st,css;
  164. st,drive = <LSEDRV_LOWEST>;
  165. };
  166. };
  167. b) for internal oscillator: "clk-hsi"
  168. Internally HSI clock is fixed to 64MHz for STM32MP157 SoC.
  169. In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC
  170. doc). So this clock frequency is used to compute the expected HSI_DIV
  171. for the clock tree initialization.
  172. Example with HSIDIV = /1:
  173. / {
  174. clocks {
  175. clk_hsi: clk-hsi {
  176. #clock-cells = <0>;
  177. compatible = "fixed-clock";
  178. clock-frequency = <64000000>;
  179. };
  180. };
  181. Example with HSIDIV = /2
  182. / {
  183. clocks {
  184. clk_hsi: clk-hsi {
  185. #clock-cells = <0>;
  186. compatible = "fixed-clock";
  187. clock-frequency = <32000000>;
  188. };
  189. };
  190. Example of clock tree initialization
  191. ====================================
  192. / {
  193. clocks {
  194. u-boot,dm-pre-reloc;
  195. clk_hse: clk-hse {
  196. u-boot,dm-pre-reloc;
  197. #clock-cells = <0>;
  198. compatible = "fixed-clock";
  199. clock-frequency = <24000000>;
  200. st,digbypass;
  201. };
  202. clk_hsi: clk-hsi {
  203. u-boot,dm-pre-reloc;
  204. #clock-cells = <0>;
  205. compatible = "fixed-clock";
  206. clock-frequency = <64000000>;
  207. };
  208. clk_lse: clk-lse {
  209. u-boot,dm-pre-reloc;
  210. #clock-cells = <0>;
  211. compatible = "fixed-clock";
  212. clock-frequency = <32768>;
  213. };
  214. clk_lsi: clk-lsi {
  215. u-boot,dm-pre-reloc;
  216. #clock-cells = <0>;
  217. compatible = "fixed-clock";
  218. clock-frequency = <32000>;
  219. };
  220. clk_csi: clk-csi {
  221. u-boot,dm-pre-reloc;
  222. #clock-cells = <0>;
  223. compatible = "fixed-clock";
  224. clock-frequency = <4000000>;
  225. };
  226. };
  227. soc {
  228. rcc: rcc@50000000 {
  229. u-boot,dm-pre-reloc;
  230. compatible = "st,stm32mp1-rcc", "syscon";
  231. reg = <0x50000000 0x1000>;
  232. #clock-cells = <1>;
  233. #reset-cells = <1>;
  234. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  235. st,clksrc = <
  236. CLK_MPU_PLL1P
  237. CLK_AXI_PLL2P
  238. CLK_MCU_PLL3P
  239. CLK_PLL12_HSE
  240. CLK_PLL3_HSE
  241. CLK_PLL4_HSE
  242. CLK_RTC_LSE
  243. CLK_MCO1_DISABLED
  244. CLK_MCO2_DISABLED
  245. >;
  246. st,clkdiv = <
  247. 1 /*MPU*/
  248. 0 /*AXI*/
  249. 0 /*MCU*/
  250. 1 /*APB1*/
  251. 1 /*APB2*/
  252. 1 /*APB3*/
  253. 1 /*APB4*/
  254. 2 /*APB5*/
  255. 23 /*RTC*/
  256. 0 /*MCO1*/
  257. 0 /*MCO2*/
  258. >;
  259. st,pkcs = <
  260. CLK_CKPER_HSE
  261. CLK_FMC_ACLK
  262. CLK_QSPI_ACLK
  263. CLK_ETH_DISABLED
  264. CLK_SDMMC12_PLL4P
  265. CLK_DSI_DSIPLL
  266. CLK_STGEN_HSE
  267. CLK_USBPHY_HSE
  268. CLK_SPI2S1_PLL3Q
  269. CLK_SPI2S23_PLL3Q
  270. CLK_SPI45_HSI
  271. CLK_SPI6_HSI
  272. CLK_I2C46_HSI
  273. CLK_SDMMC3_PLL4P
  274. CLK_USBO_USBPHY
  275. CLK_ADC_CKPER
  276. CLK_CEC_LSE
  277. CLK_I2C12_HSI
  278. CLK_I2C35_HSI
  279. CLK_UART1_HSI
  280. CLK_UART24_HSI
  281. CLK_UART35_HSI
  282. CLK_UART6_HSI
  283. CLK_UART78_HSI
  284. CLK_SPDIF_PLL4P
  285. CLK_FDCAN_PLL4Q
  286. CLK_SAI1_PLL3Q
  287. CLK_SAI2_PLL3Q
  288. CLK_SAI3_PLL3Q
  289. CLK_SAI4_PLL3Q
  290. CLK_RNG1_LSI
  291. CLK_RNG2_LSI
  292. CLK_LPTIM1_PCLK1
  293. CLK_LPTIM23_PCLK3
  294. CLK_LPTIM45_LSE
  295. >;
  296. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  297. pll1: st,pll@0 {
  298. cfg = < 2 80 0 0 0 PQR(1,0,0) >;
  299. frac = < 0x800 >;
  300. u-boot,dm-pre-reloc;
  301. };
  302. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
  303. R = 533 (DDR) */
  304. pll2: st,pll@1 {
  305. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  306. frac = < 0x1400 >;
  307. u-boot,dm-pre-reloc;
  308. };
  309. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  310. pll3: st,pll@2 {
  311. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  312. frac = < 0x1a04 >;
  313. u-boot,dm-pre-reloc;
  314. };
  315. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  316. pll4: st,pll@3 {
  317. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  318. u-boot,dm-pre-reloc;
  319. };
  320. };
  321. };
  322. };