rockchip,rk3368-dmc.txt 2.2 KB

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  1. RK3368 dynamic memory controller driver
  2. =======================================
  3. The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
  4. during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
  5. the following key configuration data:
  6. (a) a target-frequency (i.e. operating point) for the memory operation
  7. (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
  8. (c) a memory-schedule (i.e. mapping from physical addresses to the address
  9. pins of the memory bus)
  10. Required properties
  11. -------------------
  12. - compatible: "rockchip,rk3368-dmc"
  13. - reg
  14. protocol controller (PCTL) address and PHY controller (DDRPHY) address
  15. - rockchip,ddr-speed-bin
  16. the DDR3 device's speed-bin (as specified according to JESD-79)
  17. DDR3_800D (5-5-5)
  18. DDR3_800E (6-6-6)
  19. DDR3_1066E (6-6-6)
  20. DDR3_1066F (7-7-7)
  21. DDR3_1066G (8-8-8)
  22. DDR3_1333F (7-7-7)
  23. DDR3_1333G (8-8-8)
  24. DDR3_1333H (9-9-9)
  25. DDR3_1333J (10-10-10)
  26. DDR3_1600G (8-8-8)
  27. DDR3_1600H (9-9-9)
  28. DDR3_1600J (10-10-10)
  29. DDR3_1600K (11-11-11)
  30. DDR3_1866J (10-10-10)
  31. DDR3_1866K (11-11-11)
  32. DDR3_1866L (12-12-12)
  33. DDR3_1866M (13-13-13)
  34. DDR3_2133K (11-11-11)
  35. DDR3_2133L (12-12-12)
  36. DDR3_2133M (13-13-13)
  37. DDR3_2133N (14-14-14)
  38. - rockchip,ddr-frequency:
  39. target DDR clock frequency in Hz (not all frequencies may be supported,
  40. as there's some cooperation from the clock-driver required)
  41. - rockchip,memory-schedule:
  42. controls the decoding of physical addresses to DRAM addressing (i.e. how
  43. the physical address maps onto the address pins/chip-select of the device)
  44. DMC_MSCH_CBDR: column -> bank -> device -> row
  45. DMC_MSCH_CBRD: column -> band -> row -> device
  46. DMC_MSCH_CRBD: column -> row -> band -> device
  47. Example (for DDR3-1600K and 800MHz)
  48. -----------------------------------
  49. #include <dt-bindings/memory/rk3368-dmc.h>
  50. dmc: dmc@ff610000 {
  51. u-boot,dm-pre-reloc;
  52. compatible = "rockchip,rk3368-dmc";
  53. reg = <0 0xff610000 0 0x400
  54. 0 0xff620000 0 0x400>;
  55. };
  56. &dmc {
  57. rockchip,ddr-speed-bin = <DDR3_1600K>;
  58. rockchip,ddr-frequency = <800000000>;
  59. rockchip,memory-schedule = <DMC_MSCH_CBRD>;
  60. };