README.mpc85xxcds 6.1 KB

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  1. Motorola MPC85xxCDS boards
  2. --------------------------
  3. The CDS family of boards consists of a PCI backplane called the
  4. "Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot,
  5. and a CPU daughter card that bolts onto the daughter card.
  6. Much of the content of the README.mpc85xxads for the 85xx ADS boards
  7. applies to the 85xx CDS boards as well. In particular the toolchain,
  8. the switch nomenclature, and the basis for the memory map. There are
  9. some differences, though.
  10. Building U-Boot
  11. ---------------
  12. The Binutils in current ELDK toolchain will not support MPC85xx
  13. chip. You need to use binutils-2.14.tar.bz2 (or newer) from
  14. http://ftp.gnu.org/gnu/binutils.
  15. The 85xx CDS code base is known to compile using:
  16. gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
  17. Memory Map
  18. ----------
  19. The memory map for U-Boot and linux has been extended w.r.t. the ADS
  20. platform to allow for utilization of all 85xx CDS devices. The memory
  21. map is setup for linux to operate properly. The linux source when
  22. configured for MPC85xx CDS has been updated to reflect the new memory
  23. map.
  24. The mapping is:
  25. 0x0000_0000 0x7fff_ffff DDR 2G
  26. 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
  27. 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
  28. 0xe000_0000 0xe00f_ffff CCSR 1M
  29. 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
  30. 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
  31. 0xf000_0000 0xf7ff_ffff SDRAM 128M
  32. 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
  33. 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
  34. 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
  35. (*) The system control registers (CADMUS) start at offset 0xfdb0_4000
  36. within the NVRAM/CADMUS region of memory.
  37. Using Flash
  38. -----------
  39. The CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000).
  40. There is a switch which allows the boot-bank to be selected. The switch
  41. settings for updating flash are given below.
  42. The U-Boot commands for copying the boot-bank into the secondary bank are
  43. as follows:
  44. erase ff780000 ff7fffff
  45. cp.b fff80000 ff780000 80000
  46. U-Boot/kermit commands for downloading an image, then copying
  47. it into the secondary bank:
  48. loadb
  49. [Drop to kermit:
  50. ^\c
  51. send <u-boot-bin-image>
  52. c
  53. ]
  54. erase ff780000 ff7fffff
  55. cp.b $loadaddr ff780000 80000
  56. U-Boot commands for downloading an image via tftp and flashing
  57. it into the second bank:
  58. tftp 10000 <u-boot.bin.image>
  59. erase ff780000 ff7fffff
  60. cp.b 10000 ff780000 80000
  61. After copying the image into the second bank of flash, be sure to toggle
  62. SW2[2] on the carrier card before resetting the board in order to set the
  63. secondary bank as the boot-bank.
  64. Carrier Board Switches
  65. ----------------------
  66. As a reminder, you should read the README.mpc85xxads too.
  67. Most switches on the carrier board should not be changed. The only
  68. user-settable switches on the carrier board are used to configure
  69. the flash banks and determining the PCI slot.
  70. The first two bits of SW2 control how flash is used on the board:
  71. 12345678
  72. --------
  73. SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available.
  74. 01XXXXXX FLASH: Boot bank 2, bank 1 available (swapped).
  75. 10XXXXXX FLASH: Boot promjet, bank 1 available
  76. 11XXXXXX FLASH: Boot promjet, bank 2 available
  77. The boot bank is always mapped to FF80_0000 and listed first by
  78. the "flinfo" command. The secondary bank is always FF00_0000.
  79. When using PCI, linux needs to know to which slot the CDS carrier is
  80. connected.. By convention, the user-specific bits of SW2 are used to
  81. convey this information:
  82. 12345678
  83. --------
  84. SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia
  85. xxxxxx01 PCI SLOT INFORM: The CDS carrier is in slot1 of the Arcadia
  86. xxxxxx10 PCI SLOT INFORM: The CDS carrier is in slot2 of the Arcadia
  87. xxxxxx11 PCI SLOT INFORM: The CDS carrier is in slot3 of the Arcadia
  88. These are cleverly, er, clearly silkscreened as Slot 1 through 4,
  89. respectively, on the Arcadia near the support posts.
  90. The default setting of all switches on the carrier board is:
  91. 12345678
  92. --------
  93. SW1=01101100
  94. SW2=0x1111yy x=Flash bank, yy=PCI slot
  95. SW3=11101111
  96. SW4=10001000
  97. 8555/41 CPU Card Switches
  98. -------------------------
  99. Most switches on the CPU Card should not be changed. However, the
  100. frequency can be changed by setting SW3:
  101. 12345678
  102. --------
  103. SW3=XX00XXXX == CORE:CCB 2:1
  104. XX01XXXX == CORE:CCB 5:2
  105. XX10XXXX == CORE:CCB 3:1
  106. XX11XXXX == CORE:CCB 7:2
  107. XXXX1000 == CCB:SYSCLK 8:1
  108. XXXX1010 == CCB:SYSCLK 10:1
  109. A safe default setting for all switches on the CPU board is:
  110. 12345678
  111. --------
  112. SW1=10001111
  113. SW2=01000111
  114. SW3=00001000
  115. SW4=11111110
  116. 8548 CPU Card Switches
  117. ----------------------
  118. And, just to be confusing, in this set of switches:
  119. ON = 1
  120. OFF = 0
  121. Default
  122. SW1=11111101
  123. SW2=10011111
  124. SW3=11001000 (8X) (2:1)
  125. SW4=11110011
  126. SW3=X000XXXX == CORE:CCB 4:1
  127. X001XXXX == CORE:CCB 9:2
  128. X010XXXX == CORE:CCB 1:1
  129. X011XXXX == CORE:CCB 3:2
  130. X100XXXX == CORE:CCB 2:1
  131. X101XXXX == CORE:CCB 5:2
  132. X110XXXX == CORE:CCB 3:1
  133. X111XXXX == CORE:CCB 7:2
  134. XXXX0000 == CCB:SYSCLK 16:1
  135. XXXX0001 == RESERVED
  136. XXXX0010 == CCB:SYSCLK 2:1
  137. XXXX0011 == CCB:SYSCLK 3:1
  138. XXXX0100 == CCB:SYSCLK 4:1
  139. XXXX0101 == CCB:SYSCLK 5:1
  140. XXXX0110 == CCB:SYSCLK 6:1
  141. XXXX0111 == RESERVED
  142. XXXX1000 == CCB:SYSCLK 8:1
  143. XXXX1001 == CCB:SYSCLK 9:1
  144. XXXX1010 == CCB:SYSCLK 10:1
  145. XXXX1011 == RESERVED
  146. XXXX1100 == CCB:SYSCLK 12:1
  147. XXXX1101 == CCB:SYSCLK 20:1
  148. XXXX1110 == RESERVED
  149. XXXX1111 == RESERVED
  150. eDINK Info
  151. ----------
  152. One bank of flash may contain an eDINK image.
  153. Memory Map:
  154. CCSRBAR @ 0xe0000000
  155. Flash Bank 1 @ 0xfe000000
  156. Flash Bank 2 @ 0xff000000
  157. Ram @ 0
  158. Commands for downloading a U-Boot image to memory from edink:
  159. env -c
  160. time -s 4/8/2004 4:30p
  161. dl -k -b -o 100000
  162. [Drop to kermit:
  163. ^\c
  164. transmit /binary <u-boot-bin-image>
  165. c
  166. ]
  167. fu -l 100000 fe780000 80000