zynqmp.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <env.h>
  9. #include <init.h>
  10. #include <sata.h>
  11. #include <ahci.h>
  12. #include <scsi.h>
  13. #include <malloc.h>
  14. #include <wdt.h>
  15. #include <asm/arch/clk.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/arch/psu_init_gpl.h>
  19. #include <asm/io.h>
  20. #include <dm/device.h>
  21. #include <dm/uclass.h>
  22. #include <usb.h>
  23. #include <dwc3-uboot.h>
  24. #include <zynqmppl.h>
  25. #include <zynqmp_firmware.h>
  26. #include <g_dnl.h>
  27. #include <linux/sizes.h>
  28. #include "pm_cfg_obj.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  31. !defined(CONFIG_SPL_BUILD)
  32. static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  33. static const struct {
  34. u32 id;
  35. u32 ver;
  36. char *name;
  37. bool evexists;
  38. } zynqmp_devices[] = {
  39. {
  40. .id = 0x10,
  41. .name = "3eg",
  42. },
  43. {
  44. .id = 0x10,
  45. .ver = 0x2c,
  46. .name = "3cg",
  47. },
  48. {
  49. .id = 0x11,
  50. .name = "2eg",
  51. },
  52. {
  53. .id = 0x11,
  54. .ver = 0x2c,
  55. .name = "2cg",
  56. },
  57. {
  58. .id = 0x20,
  59. .name = "5ev",
  60. .evexists = 1,
  61. },
  62. {
  63. .id = 0x20,
  64. .ver = 0x100,
  65. .name = "5eg",
  66. .evexists = 1,
  67. },
  68. {
  69. .id = 0x20,
  70. .ver = 0x12c,
  71. .name = "5cg",
  72. .evexists = 1,
  73. },
  74. {
  75. .id = 0x21,
  76. .name = "4ev",
  77. .evexists = 1,
  78. },
  79. {
  80. .id = 0x21,
  81. .ver = 0x100,
  82. .name = "4eg",
  83. .evexists = 1,
  84. },
  85. {
  86. .id = 0x21,
  87. .ver = 0x12c,
  88. .name = "4cg",
  89. .evexists = 1,
  90. },
  91. {
  92. .id = 0x30,
  93. .name = "7ev",
  94. .evexists = 1,
  95. },
  96. {
  97. .id = 0x30,
  98. .ver = 0x100,
  99. .name = "7eg",
  100. .evexists = 1,
  101. },
  102. {
  103. .id = 0x30,
  104. .ver = 0x12c,
  105. .name = "7cg",
  106. .evexists = 1,
  107. },
  108. {
  109. .id = 0x38,
  110. .name = "9eg",
  111. },
  112. {
  113. .id = 0x38,
  114. .ver = 0x2c,
  115. .name = "9cg",
  116. },
  117. {
  118. .id = 0x39,
  119. .name = "6eg",
  120. },
  121. {
  122. .id = 0x39,
  123. .ver = 0x2c,
  124. .name = "6cg",
  125. },
  126. {
  127. .id = 0x40,
  128. .name = "11eg",
  129. },
  130. { /* For testing purpose only */
  131. .id = 0x50,
  132. .ver = 0x2c,
  133. .name = "15cg",
  134. },
  135. {
  136. .id = 0x50,
  137. .name = "15eg",
  138. },
  139. {
  140. .id = 0x58,
  141. .name = "19eg",
  142. },
  143. {
  144. .id = 0x59,
  145. .name = "17eg",
  146. },
  147. {
  148. .id = 0x61,
  149. .name = "21dr",
  150. },
  151. {
  152. .id = 0x63,
  153. .name = "23dr",
  154. },
  155. {
  156. .id = 0x65,
  157. .name = "25dr",
  158. },
  159. {
  160. .id = 0x64,
  161. .name = "27dr",
  162. },
  163. {
  164. .id = 0x60,
  165. .name = "28dr",
  166. },
  167. {
  168. .id = 0x62,
  169. .name = "29dr",
  170. },
  171. {
  172. .id = 0x66,
  173. .name = "39dr",
  174. },
  175. {
  176. .id = 0x7b,
  177. .name = "48dr",
  178. },
  179. {
  180. .id = 0x7e,
  181. .name = "49dr",
  182. },
  183. };
  184. #endif
  185. int chip_id(unsigned char id)
  186. {
  187. struct pt_regs regs;
  188. int val = -EINVAL;
  189. if (current_el() != 3) {
  190. regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
  191. regs.regs[1] = 0;
  192. regs.regs[2] = 0;
  193. regs.regs[3] = 0;
  194. smc_call(&regs);
  195. /*
  196. * SMC returns:
  197. * regs[0][31:0] = status of the operation
  198. * regs[0][63:32] = CSU.IDCODE register
  199. * regs[1][31:0] = CSU.version register
  200. * regs[1][63:32] = CSU.IDCODE2 register
  201. */
  202. switch (id) {
  203. case IDCODE:
  204. regs.regs[0] = upper_32_bits(regs.regs[0]);
  205. regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  206. ZYNQMP_CSU_IDCODE_SVD_MASK;
  207. regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  208. val = regs.regs[0];
  209. break;
  210. case VERSION:
  211. regs.regs[1] = lower_32_bits(regs.regs[1]);
  212. regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
  213. val = regs.regs[1];
  214. break;
  215. case IDCODE2:
  216. regs.regs[1] = lower_32_bits(regs.regs[1]);
  217. regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
  218. val = regs.regs[1];
  219. break;
  220. default:
  221. printf("%s, Invalid Req:0x%x\n", __func__, id);
  222. }
  223. } else {
  224. switch (id) {
  225. case IDCODE:
  226. val = readl(ZYNQMP_CSU_IDCODE_ADDR);
  227. val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  228. ZYNQMP_CSU_IDCODE_SVD_MASK;
  229. val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  230. break;
  231. case VERSION:
  232. val = readl(ZYNQMP_CSU_VER_ADDR);
  233. val &= ZYNQMP_CSU_SILICON_VER_MASK;
  234. break;
  235. default:
  236. printf("%s, Invalid Req:0x%x\n", __func__, id);
  237. }
  238. }
  239. return val;
  240. }
  241. #define ZYNQMP_VERSION_SIZE 9
  242. #define ZYNQMP_PL_STATUS_BIT 9
  243. #define ZYNQMP_IPDIS_VCU_BIT 8
  244. #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
  245. #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
  246. #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
  247. ~BIT(ZYNQMP_IPDIS_VCU_BIT)
  248. #define MAX_VARIANTS_EV 3
  249. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  250. !defined(CONFIG_SPL_BUILD)
  251. static char *zynqmp_get_silicon_idcode_name(void)
  252. {
  253. u32 i, id, ver, j;
  254. char *buf;
  255. static char name[ZYNQMP_VERSION_SIZE];
  256. id = chip_id(IDCODE);
  257. ver = chip_id(IDCODE2);
  258. for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
  259. if (zynqmp_devices[i].id == id) {
  260. if (zynqmp_devices[i].evexists &&
  261. !(ver & ZYNQMP_PL_STATUS_MASK))
  262. break;
  263. if (zynqmp_devices[i].ver == (ver &
  264. ZYNQMP_CSU_VERSION_MASK))
  265. break;
  266. }
  267. }
  268. if (i >= ARRAY_SIZE(zynqmp_devices))
  269. return "unknown";
  270. strncat(name, "zu", 2);
  271. if (!zynqmp_devices[i].evexists ||
  272. (ver & ZYNQMP_PL_STATUS_MASK)) {
  273. strncat(name, zynqmp_devices[i].name,
  274. ZYNQMP_VERSION_SIZE - 3);
  275. return name;
  276. }
  277. /*
  278. * Here we are means, PL not powered up and ev variant
  279. * exists. So, we need to ignore VCU disable bit(8) in
  280. * version and findout if its CG or EG/EV variant.
  281. */
  282. for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
  283. if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
  284. (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
  285. strncat(name, zynqmp_devices[i].name,
  286. ZYNQMP_VERSION_SIZE - 3);
  287. break;
  288. }
  289. }
  290. if (j >= MAX_VARIANTS_EV)
  291. return "unknown";
  292. if (strstr(name, "eg") || strstr(name, "ev")) {
  293. buf = strstr(name, "e");
  294. *buf = '\0';
  295. }
  296. return name;
  297. }
  298. #endif
  299. int board_early_init_f(void)
  300. {
  301. int ret = 0;
  302. #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
  303. ret = psu_init();
  304. #endif
  305. return ret;
  306. }
  307. int board_init(void)
  308. {
  309. struct udevice *dev;
  310. uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
  311. if (!dev)
  312. panic("PMU Firmware device not found - Enable it");
  313. #if defined(CONFIG_SPL_BUILD)
  314. /* Check *at build time* if the filename is an non-empty string */
  315. if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
  316. zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
  317. zynqmp_pm_cfg_obj_size);
  318. #endif
  319. printf("EL Level:\tEL%d\n", current_el());
  320. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  321. !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
  322. defined(CONFIG_SPL_BUILD))
  323. if (current_el() != 3) {
  324. zynqmppl.name = zynqmp_get_silicon_idcode_name();
  325. printf("Chip ID:\t%s\n", zynqmppl.name);
  326. fpga_init();
  327. fpga_add(fpga_xilinx, &zynqmppl);
  328. }
  329. #endif
  330. return 0;
  331. }
  332. int board_early_init_r(void)
  333. {
  334. u32 val;
  335. if (current_el() != 3)
  336. return 0;
  337. val = readl(&crlapb_base->timestamp_ref_ctrl);
  338. val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  339. if (!val) {
  340. val = readl(&crlapb_base->timestamp_ref_ctrl);
  341. val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  342. writel(val, &crlapb_base->timestamp_ref_ctrl);
  343. /* Program freq register in System counter */
  344. writel(zynqmp_get_system_timer_freq(),
  345. &iou_scntr_secure->base_frequency_id_register);
  346. /* And enable system counter */
  347. writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
  348. &iou_scntr_secure->counter_control_register);
  349. }
  350. return 0;
  351. }
  352. unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
  353. char * const argv[])
  354. {
  355. int ret = 0;
  356. if (current_el() > 1) {
  357. smp_kick_all_cpus();
  358. dcache_disable();
  359. armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
  360. ES_TO_AARCH64);
  361. } else {
  362. printf("FAIL: current EL is not above EL1\n");
  363. ret = EINVAL;
  364. }
  365. return ret;
  366. }
  367. #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
  368. int dram_init_banksize(void)
  369. {
  370. int ret;
  371. ret = fdtdec_setup_memory_banksize();
  372. if (ret)
  373. return ret;
  374. mem_map_fill();
  375. return 0;
  376. }
  377. int dram_init(void)
  378. {
  379. if (fdtdec_setup_mem_size_base() != 0)
  380. return -EINVAL;
  381. return 0;
  382. }
  383. #else
  384. int dram_init_banksize(void)
  385. {
  386. #if defined(CONFIG_NR_DRAM_BANKS)
  387. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  388. gd->bd->bi_dram[0].size = get_effective_memsize();
  389. #endif
  390. mem_map_fill();
  391. return 0;
  392. }
  393. int dram_init(void)
  394. {
  395. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  396. CONFIG_SYS_SDRAM_SIZE);
  397. return 0;
  398. }
  399. #endif
  400. void reset_cpu(ulong addr)
  401. {
  402. }
  403. #if defined(CONFIG_BOARD_LATE_INIT)
  404. static const struct {
  405. u32 bit;
  406. const char *name;
  407. } reset_reasons[] = {
  408. { RESET_REASON_DEBUG_SYS, "DEBUG" },
  409. { RESET_REASON_SOFT, "SOFT" },
  410. { RESET_REASON_SRST, "SRST" },
  411. { RESET_REASON_PSONLY, "PS-ONLY" },
  412. { RESET_REASON_PMU, "PMU" },
  413. { RESET_REASON_INTERNAL, "INTERNAL" },
  414. { RESET_REASON_EXTERNAL, "EXTERNAL" },
  415. {}
  416. };
  417. static int reset_reason(void)
  418. {
  419. u32 reg;
  420. int i, ret;
  421. const char *reason = NULL;
  422. ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
  423. if (ret)
  424. return -EINVAL;
  425. puts("Reset reason:\t");
  426. for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
  427. if (reg & reset_reasons[i].bit) {
  428. reason = reset_reasons[i].name;
  429. printf("%s ", reset_reasons[i].name);
  430. break;
  431. }
  432. }
  433. puts("\n");
  434. env_set("reset_reason", reason);
  435. ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
  436. if (ret)
  437. return -EINVAL;
  438. return ret;
  439. }
  440. static int set_fdtfile(void)
  441. {
  442. char *compatible, *fdtfile;
  443. const char *suffix = ".dtb";
  444. const char *vendor = "xilinx/";
  445. if (env_get("fdtfile"))
  446. return 0;
  447. compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
  448. if (compatible) {
  449. debug("Compatible: %s\n", compatible);
  450. /* Discard vendor prefix */
  451. strsep(&compatible, ",");
  452. fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
  453. strlen(suffix) + 1);
  454. if (!fdtfile)
  455. return -ENOMEM;
  456. sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
  457. env_set("fdtfile", fdtfile);
  458. free(fdtfile);
  459. }
  460. return 0;
  461. }
  462. int board_late_init(void)
  463. {
  464. u32 reg = 0;
  465. u8 bootmode;
  466. struct udevice *dev;
  467. int bootseq = -1;
  468. int bootseq_len = 0;
  469. int env_targets_len = 0;
  470. const char *mode;
  471. char *new_targets;
  472. char *env_targets;
  473. int ret;
  474. ulong initrd_hi;
  475. #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
  476. usb_ether_init();
  477. #endif
  478. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  479. debug("Saved variables - Skipping\n");
  480. return 0;
  481. }
  482. ret = set_fdtfile();
  483. if (ret)
  484. return ret;
  485. ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
  486. if (ret)
  487. return -EINVAL;
  488. if (reg >> BOOT_MODE_ALT_SHIFT)
  489. reg >>= BOOT_MODE_ALT_SHIFT;
  490. bootmode = reg & BOOT_MODES_MASK;
  491. puts("Bootmode: ");
  492. switch (bootmode) {
  493. case USB_MODE:
  494. puts("USB_MODE\n");
  495. mode = "usb";
  496. env_set("modeboot", "usb_dfu_spl");
  497. break;
  498. case JTAG_MODE:
  499. puts("JTAG_MODE\n");
  500. mode = "jtag pxe dhcp";
  501. env_set("modeboot", "jtagboot");
  502. break;
  503. case QSPI_MODE_24BIT:
  504. case QSPI_MODE_32BIT:
  505. mode = "qspi0";
  506. puts("QSPI_MODE\n");
  507. env_set("modeboot", "qspiboot");
  508. break;
  509. case EMMC_MODE:
  510. puts("EMMC_MODE\n");
  511. mode = "mmc0";
  512. env_set("modeboot", "emmcboot");
  513. break;
  514. case SD_MODE:
  515. puts("SD_MODE\n");
  516. if (uclass_get_device_by_name(UCLASS_MMC,
  517. "mmc@ff160000", &dev) &&
  518. uclass_get_device_by_name(UCLASS_MMC,
  519. "sdhci@ff160000", &dev)) {
  520. puts("Boot from SD0 but without SD0 enabled!\n");
  521. return -1;
  522. }
  523. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  524. mode = "mmc";
  525. bootseq = dev->seq;
  526. env_set("modeboot", "sdboot");
  527. break;
  528. case SD1_LSHFT_MODE:
  529. puts("LVL_SHFT_");
  530. /* fall through */
  531. case SD_MODE1:
  532. puts("SD_MODE1\n");
  533. if (uclass_get_device_by_name(UCLASS_MMC,
  534. "mmc@ff170000", &dev) &&
  535. uclass_get_device_by_name(UCLASS_MMC,
  536. "sdhci@ff170000", &dev)) {
  537. puts("Boot from SD1 but without SD1 enabled!\n");
  538. return -1;
  539. }
  540. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  541. mode = "mmc";
  542. bootseq = dev->seq;
  543. env_set("modeboot", "sdboot");
  544. break;
  545. case NAND_MODE:
  546. puts("NAND_MODE\n");
  547. mode = "nand0";
  548. env_set("modeboot", "nandboot");
  549. break;
  550. default:
  551. mode = "";
  552. printf("Invalid Boot Mode:0x%x\n", bootmode);
  553. break;
  554. }
  555. if (bootseq >= 0) {
  556. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  557. debug("Bootseq len: %x\n", bootseq_len);
  558. }
  559. /*
  560. * One terminating char + one byte for space between mode
  561. * and default boot_targets
  562. */
  563. env_targets = env_get("boot_targets");
  564. if (env_targets)
  565. env_targets_len = strlen(env_targets);
  566. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  567. bootseq_len);
  568. if (!new_targets)
  569. return -ENOMEM;
  570. if (bootseq >= 0)
  571. sprintf(new_targets, "%s%x %s", mode, bootseq,
  572. env_targets ? env_targets : "");
  573. else
  574. sprintf(new_targets, "%s %s", mode,
  575. env_targets ? env_targets : "");
  576. env_set("boot_targets", new_targets);
  577. initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
  578. initrd_hi = round_down(initrd_hi, SZ_16M);
  579. env_set_addr("initrd_high", (void *)initrd_hi);
  580. reset_reason();
  581. return 0;
  582. }
  583. #endif
  584. int checkboard(void)
  585. {
  586. puts("Board: Xilinx ZynqMP\n");
  587. return 0;
  588. }