ddr.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fsl_ddr_sdram.h>
  8. #include <fsl_ddr_dimm_params.h>
  9. void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
  10. {
  11. i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
  12. /* We use soldered memory, but use an SPD EEPROM to describe it.
  13. * The SPD has an unspecified dimm type, but the DDR2 initialization
  14. * code requires a specific type to be specified. This sets the type
  15. * as a standard unregistered SO-DIMM. */
  16. if (spd->dimm_type == 0) {
  17. spd->dimm_type = 0x4;
  18. ((uchar *)spd)[63] += 0x4;
  19. }
  20. }
  21. void fsl_ddr_board_options(memctl_options_t *popts,
  22. dimm_params_t *pdimm,
  23. unsigned int ctrl_num)
  24. {
  25. /*
  26. * Factors to consider for clock adjust:
  27. * - number of chips on bus
  28. * - position of slot
  29. * - DDR1 vs. DDR2?
  30. * - ???
  31. *
  32. * This needs to be determined on a board-by-board basis.
  33. * 0110 3/4 cycle late
  34. * 0111 7/8 cycle late
  35. */
  36. popts->clk_adjust = 7;
  37. /*
  38. * Factors to consider for CPO:
  39. * - frequency
  40. * - ddr1 vs. ddr2
  41. */
  42. popts->cpo_override = 9;
  43. /*
  44. * Factors to consider for write data delay:
  45. * - number of DIMMs
  46. *
  47. * 1 = 1/4 clock delay
  48. * 2 = 1/2 clock delay
  49. * 3 = 3/4 clock delay
  50. * 4 = 1 clock delay
  51. * 5 = 5/4 clock delay
  52. * 6 = 3/2 clock delay
  53. */
  54. popts->write_data_delay = 3;
  55. /*
  56. * Factors to consider for half-strength driver enable:
  57. * - number of DIMMs installed
  58. */
  59. popts->half_strength_driver_enable = 0;
  60. }