ddr.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009 Extreme Engineering Solutions, Inc.
  4. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <fsl_ddr_dimm_params.h>
  10. void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
  11. {
  12. i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
  13. sizeof(ddr2_spd_eeprom_t));
  14. }
  15. /*
  16. * There are four board-specific SDRAM timing parameters which must be
  17. * calculated based on the particular PCB artwork. These are:
  18. * 1.) CPO (Read Capture Delay)
  19. * - TIMING_CFG_2 register
  20. * Source: Calculation based on board trace lengths and
  21. * chip-specific internal delays.
  22. * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
  23. * - TIMING_CFG_2 register
  24. * Source: Calculation based on board trace lengths.
  25. * Unless clock and DQ lanes are very different
  26. * lengths (>2"), this should be set to the nominal value
  27. * of 1/2 clock delay.
  28. * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
  29. * - DDR_SDRAM_CLK_CNTL register
  30. * Source: Signal Integrity Simulations
  31. * 4.) 2T Timing on Addr/Ctl
  32. * - TIMING_CFG_2 register
  33. * Source: Signal Integrity Simulations
  34. * Usually only needed with heavy load/very high speed (>DDR2-800)
  35. *
  36. * PCB routing on the XPedite5170 is nearly identical to the XPedite5370
  37. * so we use the XPedite5370 settings as a basis for the XPedite5170.
  38. */
  39. typedef struct board_memctl_options {
  40. uint16_t datarate_mhz_low;
  41. uint16_t datarate_mhz_high;
  42. uint8_t clk_adjust;
  43. uint8_t cpo_override;
  44. uint8_t write_data_delay;
  45. } board_memctl_options_t;
  46. static struct board_memctl_options bopts_ctrl[][2] = {
  47. {
  48. /* Controller 0 */
  49. {
  50. /* DDR2 600/667 */
  51. .datarate_mhz_low = 500,
  52. .datarate_mhz_high = 750,
  53. .clk_adjust = 5,
  54. .cpo_override = 8,
  55. .write_data_delay = 2,
  56. },
  57. {
  58. /* DDR2 800 */
  59. .datarate_mhz_low = 750,
  60. .datarate_mhz_high = 850,
  61. .clk_adjust = 5,
  62. .cpo_override = 9,
  63. .write_data_delay = 2,
  64. },
  65. },
  66. {
  67. /* Controller 1 */
  68. {
  69. /* DDR2 600/667 */
  70. .datarate_mhz_low = 500,
  71. .datarate_mhz_high = 750,
  72. .clk_adjust = 5,
  73. .cpo_override = 7,
  74. .write_data_delay = 2,
  75. },
  76. {
  77. /* DDR2 800 */
  78. .datarate_mhz_low = 750,
  79. .datarate_mhz_high = 850,
  80. .clk_adjust = 5,
  81. .cpo_override = 8,
  82. .write_data_delay = 2,
  83. },
  84. },
  85. };
  86. void fsl_ddr_board_options(memctl_options_t *popts,
  87. dimm_params_t *pdimm,
  88. unsigned int ctrl_num)
  89. {
  90. struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
  91. sys_info_t sysinfo;
  92. int i;
  93. unsigned int datarate;
  94. get_sys_info(&sysinfo);
  95. datarate = get_ddr_freq(0) / 1000000;
  96. for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
  97. if ((bopts[i].datarate_mhz_low <= datarate) &&
  98. (bopts[i].datarate_mhz_high >= datarate)) {
  99. debug("controller %d:\n", ctrl_num);
  100. debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
  101. debug(" cpo = %d\n", bopts[i].cpo_override);
  102. debug(" write_data_delay = %d\n",
  103. bopts[i].write_data_delay);
  104. popts->clk_adjust = bopts[i].clk_adjust;
  105. popts->cpo_override = bopts[i].cpo_override;
  106. popts->write_data_delay = bopts[i].write_data_delay;
  107. }
  108. }
  109. /*
  110. * Factors to consider for half-strength driver enable:
  111. * - number of DIMMs installed
  112. */
  113. popts->half_strength_driver_enable = 0;
  114. }