woodburn.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
  4. *
  5. * Based on flea3.c and mx35pdk.c
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <linux/errno.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/iomux-mx35.h>
  14. #include <i2c.h>
  15. #include <power/pmic.h>
  16. #include <fsl_pmic.h>
  17. #include <mc13892.h>
  18. #include <mmc.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <linux/types.h>
  21. #include <asm/gpio.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <netdev.h>
  24. #include <spl.h>
  25. #define CCM_CCMR_CONFIG 0x003F4208
  26. #define ESDCTL_DDR2_CONFIG 0x007FFC3F
  27. /* For MMC */
  28. #define GPIO_MMC_CD 7
  29. #define GPIO_MMC_WP 8
  30. DECLARE_GLOBAL_DATA_PTR;
  31. int dram_init(void)
  32. {
  33. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
  34. PHYS_SDRAM_1_SIZE);
  35. return 0;
  36. }
  37. static void board_setup_sdram(void)
  38. {
  39. struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  40. /* Initialize with default values both CSD0/1 */
  41. writel(0x2000, &esdc->esdctl0);
  42. writel(0x2000, &esdc->esdctl1);
  43. mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
  44. 13, 10, 2, 0x8080);
  45. }
  46. static void setup_iomux_fec(void)
  47. {
  48. static const iomux_v3_cfg_t fec_pads[] = {
  49. MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
  50. MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
  51. MX35_PAD_FEC_RX_DV__FEC_RX_DV,
  52. MX35_PAD_FEC_COL__FEC_COL,
  53. MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
  54. MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
  55. MX35_PAD_FEC_TX_EN__FEC_TX_EN,
  56. MX35_PAD_FEC_MDC__FEC_MDC,
  57. MX35_PAD_FEC_MDIO__FEC_MDIO,
  58. MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
  59. MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
  60. MX35_PAD_FEC_CRS__FEC_CRS,
  61. MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
  62. MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
  63. MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
  64. MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
  65. MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
  66. MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
  67. };
  68. /* setup pins for FEC */
  69. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  70. }
  71. int woodburn_init(void)
  72. {
  73. struct ccm_regs *ccm =
  74. (struct ccm_regs *)IMX_CCM_BASE;
  75. /* initialize PLL and clock configuration */
  76. writel(CCM_CCMR_CONFIG, &ccm->ccmr);
  77. /* Set-up RAM */
  78. board_setup_sdram();
  79. /* enable clocks */
  80. writel(readl(&ccm->cgr0) |
  81. MXC_CCM_CGR0_EMI_MASK |
  82. MXC_CCM_CGR0_EDIO_MASK |
  83. MXC_CCM_CGR0_EPIT1_MASK,
  84. &ccm->cgr0);
  85. writel(readl(&ccm->cgr1) |
  86. MXC_CCM_CGR1_FEC_MASK |
  87. MXC_CCM_CGR1_GPIO1_MASK |
  88. MXC_CCM_CGR1_GPIO2_MASK |
  89. MXC_CCM_CGR1_GPIO3_MASK |
  90. MXC_CCM_CGR1_I2C1_MASK |
  91. MXC_CCM_CGR1_I2C2_MASK |
  92. MXC_CCM_CGR1_I2C3_MASK,
  93. &ccm->cgr1);
  94. /* Set-up NAND */
  95. __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
  96. /* Set pinmux for the required peripherals */
  97. setup_iomux_fec();
  98. /* setup GPIO1_4 FEC_ENABLE signal */
  99. imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
  100. gpio_direction_output(4, 1);
  101. imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
  102. gpio_direction_output(9, 1);
  103. return 0;
  104. }
  105. #if defined(CONFIG_SPL_BUILD)
  106. void board_init_f(ulong dummy)
  107. {
  108. /* Set the stack pointer. */
  109. asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
  110. /* Initialize MUX and SDRAM */
  111. woodburn_init();
  112. /* Clear the BSS. */
  113. memset(__bss_start, 0, __bss_end - __bss_start);
  114. preloader_console_init();
  115. timer_init();
  116. board_init_r(NULL, 0);
  117. }
  118. void spl_board_init(void)
  119. {
  120. }
  121. #endif
  122. /* Booting from NOR in external mode */
  123. int board_early_init_f(void)
  124. {
  125. return woodburn_init();
  126. }
  127. int board_init(void)
  128. {
  129. struct pmic *p;
  130. u32 val;
  131. int ret;
  132. /* address of boot parameters */
  133. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  134. ret = pmic_init(I2C_PMIC);
  135. if (ret)
  136. return ret;
  137. p = pmic_get("FSL_PMIC");
  138. /*
  139. * Set switchers in Auto in NORMAL mode & STANDBY mode
  140. * Setup the switcher mode for SW1 & SW2
  141. */
  142. pmic_reg_read(p, REG_SW_4, &val);
  143. val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
  144. (SWMODE_MASK << SWMODE2_SHIFT)));
  145. val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
  146. (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
  147. /* Set SWILIMB */
  148. val |= (1 << 22);
  149. pmic_reg_write(p, REG_SW_4, val);
  150. /* Setup the switcher mode for SW3 & SW4 */
  151. pmic_reg_read(p, REG_SW_5, &val);
  152. val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
  153. (SWMODE_MASK << SWMODE3_SHIFT));
  154. val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
  155. (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
  156. pmic_reg_write(p, REG_SW_5, val);
  157. /* Set VGEN1 to 3.15V */
  158. pmic_reg_read(p, REG_SETTING_0, &val);
  159. val &= ~(VGEN1_MASK);
  160. val |= VGEN1_3_15;
  161. pmic_reg_write(p, REG_SETTING_0, val);
  162. pmic_reg_read(p, REG_MODE_0, &val);
  163. val |= VGEN1EN;
  164. pmic_reg_write(p, REG_MODE_0, val);
  165. udelay(2000);
  166. return 0;
  167. }
  168. #if defined(CONFIG_FSL_ESDHC_IMX)
  169. struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
  170. int board_mmc_init(bd_t *bis)
  171. {
  172. static const iomux_v3_cfg_t sdhc1_pads[] = {
  173. MX35_PAD_SD1_CMD__ESDHC1_CMD,
  174. MX35_PAD_SD1_CLK__ESDHC1_CLK,
  175. MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
  176. MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
  177. MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
  178. MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
  179. };
  180. /* configure pins for SDHC1 only */
  181. imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
  182. /* MMC Card Detect on GPIO1_7 */
  183. imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
  184. gpio_direction_input(GPIO_MMC_CD);
  185. /* MMC Write Protection on GPIO1_8 */
  186. imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
  187. gpio_direction_input(GPIO_MMC_WP);
  188. esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  189. return fsl_esdhc_initialize(bis, &esdhc_cfg);
  190. }
  191. int board_mmc_getcd(struct mmc *mmc)
  192. {
  193. return !gpio_get_value(GPIO_MMC_CD);
  194. }
  195. #endif
  196. u32 get_board_rev(void)
  197. {
  198. int rev = 0;
  199. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  200. }