tqma6_mba6.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5. *
  6. * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
  7. * Author: Markus Niebel <markus.niebel@tq-group.com>
  8. */
  9. #include <init.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <linux/errno.h>
  17. #include <asm/gpio.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <common.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <linux/libfdt.h>
  22. #include <malloc.h>
  23. #include <i2c.h>
  24. #include <micrel.h>
  25. #include <miiphy.h>
  26. #include <mmc.h>
  27. #include <netdev.h>
  28. #include "tqma6_bb.h"
  29. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  30. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  31. #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  32. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  34. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  35. #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  36. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  37. #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  38. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  39. #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  40. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42. PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
  43. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  44. #if defined(CONFIG_TQMA6Q)
  45. #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
  46. #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
  47. #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
  48. #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
  49. #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
  50. #else
  51. #error "need to select module"
  52. #endif
  53. #define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm)
  54. #define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
  55. #define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
  56. PAD_CTL_DSE_34ohm)
  57. #define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  58. PAD_CTL_DSE_60ohm)
  59. /* disable on die termination for RGMII */
  60. #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
  61. /* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
  62. #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
  63. /* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
  64. #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
  65. #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
  66. static iomux_v3_cfg_t const mba6_enet_pads[] = {
  67. NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL),
  68. NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL),
  69. NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL),
  70. NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL),
  71. NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL),
  72. NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL),
  73. NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL),
  74. NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
  75. ENET_TX_PAD_CTRL),
  76. NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
  77. /*
  78. * these pins are also used for config strapping by phy
  79. */
  80. NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL),
  81. NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL),
  82. NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL),
  83. NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL),
  84. NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL),
  85. NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
  86. ENET_RX_PAD_CTRL),
  87. /* KSZ9031 PHY Reset */
  88. NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL),
  89. };
  90. static void mba6_setup_iomuxc_enet(void)
  91. {
  92. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  93. /* clear gpr1[ENET_CLK_SEL] for externel clock */
  94. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  95. __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
  96. (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
  97. __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
  98. (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
  99. imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
  100. ARRAY_SIZE(mba6_enet_pads));
  101. /* Reset PHY */
  102. gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
  103. /* Need delay 10ms after power on according to KSZ9031 spec */
  104. mdelay(10);
  105. gpio_set_value(ENET_PHY_RESET_GPIO, 1);
  106. /*
  107. * KSZ9031 manual: 100 usec wait time after reset before communication
  108. * over MDIO
  109. * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
  110. * reset before the phy sees a high level
  111. */
  112. mdelay(15);
  113. }
  114. static iomux_v3_cfg_t const mba6_uart2_pads[] = {
  115. NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
  116. NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
  117. };
  118. static void mba6_setup_iomuxc_uart(void)
  119. {
  120. imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
  121. ARRAY_SIZE(mba6_uart2_pads));
  122. }
  123. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  124. #define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
  125. int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
  126. {
  127. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  128. int ret = 0;
  129. if (cfg->esdhc_base == USDHC2_BASE_ADDR)
  130. ret = !gpio_get_value(USDHC2_CD_GPIO);
  131. return ret;
  132. }
  133. int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
  134. {
  135. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  136. int ret = 0;
  137. if (cfg->esdhc_base == USDHC2_BASE_ADDR)
  138. ret = gpio_get_value(USDHC2_WP_GPIO);
  139. return ret;
  140. }
  141. static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
  142. .esdhc_base = USDHC2_BASE_ADDR,
  143. .max_bus_width = 4,
  144. };
  145. static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
  146. NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL),
  147. NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
  148. NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
  149. NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
  150. NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
  151. NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
  152. /* CD */
  153. NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL),
  154. /* WP */
  155. NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL),
  156. };
  157. int tqma6_bb_board_mmc_init(bd_t *bis)
  158. {
  159. imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
  160. ARRAY_SIZE(mba6_usdhc2_pads));
  161. gpio_direction_input(USDHC2_CD_GPIO);
  162. gpio_direction_input(USDHC2_WP_GPIO);
  163. mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  164. if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
  165. puts("Warning: failed to initialize SD\n");
  166. return 0;
  167. }
  168. static struct i2c_pads_info mba6_i2c1_pads = {
  169. /* I2C1: MBa6x */
  170. .scl = {
  171. .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
  172. I2C_PAD_CTRL),
  173. .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
  174. I2C_PAD_CTRL),
  175. .gp = IMX_GPIO_NR(5, 27)
  176. },
  177. .sda = {
  178. .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
  179. I2C_PAD_CTRL),
  180. .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
  181. I2C_PAD_CTRL),
  182. .gp = IMX_GPIO_NR(5, 26)
  183. }
  184. };
  185. static void mba6_setup_i2c(void)
  186. {
  187. int ret;
  188. /*
  189. * use logical index for bus, e.g. I2C1 -> 0
  190. * warn on error
  191. */
  192. ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
  193. if (ret)
  194. printf("setup I2C1 failed: %d\n", ret);
  195. }
  196. int board_phy_config(struct phy_device *phydev)
  197. {
  198. /*
  199. * optimized pad skew values depends on CPU variant on the TQMa6x module:
  200. * CONFIG_TQMA6Q: i.MX6Q/D
  201. * CONFIG_TQMA6S: i.MX6S
  202. * CONFIG_TQMA6DL: i.MX6DL
  203. */
  204. #if defined(CONFIG_TQMA6Q)
  205. #define MBA6X_KSZ9031_CTRL_SKEW 0x0032
  206. #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
  207. #define MBA6X_KSZ9031_RX_SKEW 0x3333
  208. #define MBA6X_KSZ9031_TX_SKEW 0x2036
  209. #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
  210. #define MBA6X_KSZ9031_CTRL_SKEW 0x0030
  211. #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
  212. #define MBA6X_KSZ9031_RX_SKEW 0x3333
  213. #define MBA6X_KSZ9031_TX_SKEW 0x2052
  214. #else
  215. #error
  216. #endif
  217. /* min rx/tx ctrl delay */
  218. ksz9031_phy_extended_write(phydev, 2,
  219. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  220. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  221. MBA6X_KSZ9031_CTRL_SKEW);
  222. /* min rx delay */
  223. ksz9031_phy_extended_write(phydev, 2,
  224. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  225. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  226. MBA6X_KSZ9031_RX_SKEW);
  227. /* max tx delay */
  228. ksz9031_phy_extended_write(phydev, 2,
  229. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  230. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  231. MBA6X_KSZ9031_TX_SKEW);
  232. /* rx/tx clk skew */
  233. ksz9031_phy_extended_write(phydev, 2,
  234. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  235. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  236. MBA6X_KSZ9031_CLK_SKEW);
  237. phydev->drv->config(phydev);
  238. return 0;
  239. }
  240. int board_eth_init(bd_t *bis)
  241. {
  242. uint32_t base = IMX_FEC_BASE;
  243. struct mii_dev *bus = NULL;
  244. struct phy_device *phydev = NULL;
  245. int ret;
  246. bus = fec_get_miibus(base, -1);
  247. if (!bus)
  248. return -EINVAL;
  249. /* scan phy */
  250. phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
  251. PHY_INTERFACE_MODE_RGMII);
  252. if (!phydev) {
  253. ret = -EINVAL;
  254. goto free_bus;
  255. }
  256. ret = fec_probe(bis, -1, base, bus, phydev);
  257. if (ret)
  258. goto free_phydev;
  259. return 0;
  260. free_phydev:
  261. free(phydev);
  262. free_bus:
  263. free(bus);
  264. return ret;
  265. }
  266. int tqma6_bb_board_early_init_f(void)
  267. {
  268. mba6_setup_iomuxc_uart();
  269. return 0;
  270. }
  271. int tqma6_bb_board_init(void)
  272. {
  273. mba6_setup_i2c();
  274. /* do it here - to have reset completed */
  275. mba6_setup_iomuxc_enet();
  276. return 0;
  277. }
  278. int tqma6_bb_board_late_init(void)
  279. {
  280. return 0;
  281. }
  282. const char *tqma6_bb_get_boardname(void)
  283. {
  284. return "MBa6x";
  285. }
  286. /*
  287. * Device Tree Support
  288. */
  289. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  290. void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
  291. {
  292. /* TBD */
  293. }
  294. #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */