pci.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2005
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  6. */
  7. #include <init.h>
  8. #include <asm/mmu.h>
  9. #include <asm/io.h>
  10. #include <common.h>
  11. #include <mpc83xx.h>
  12. #include <pci.h>
  13. #include <i2c.h>
  14. #include <asm/fsl_i2c.h>
  15. static struct pci_region pci1_regions[] = {
  16. {
  17. bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  18. phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  19. size: CONFIG_SYS_PCI1_MEM_SIZE,
  20. flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  21. },
  22. {
  23. bus_start: CONFIG_SYS_PCI1_IO_BASE,
  24. phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  25. size: CONFIG_SYS_PCI1_IO_SIZE,
  26. flags: PCI_REGION_IO
  27. },
  28. {
  29. bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  30. phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  31. size: CONFIG_SYS_PCI1_MMIO_SIZE,
  32. flags: PCI_REGION_MEM
  33. },
  34. };
  35. /*
  36. * pci_init_board()
  37. *
  38. * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
  39. * per TQM834x design physical connections to external devices (PCI sockets)
  40. * are routed only to the PCI1 we do not account for the second one - this code
  41. * supports PCI1 module only. Should support for the PCI2 be required in the
  42. * future it needs a separate pci_controller structure (above) and handling -
  43. * please refer to other boards' implementation for dual PCI host controllers,
  44. * for example board/Marvell/db64360/pci.c, pci_init_board()
  45. *
  46. */
  47. void
  48. pci_init_board(void)
  49. {
  50. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  51. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  52. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  53. struct pci_region *reg[] = { pci1_regions };
  54. u32 reg32;
  55. /*
  56. * Configure PCI controller and PCI_CLK_OUTPUT
  57. *
  58. * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
  59. * line actually used for clocking all external PCI devices in TQM83xx.
  60. * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
  61. * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
  62. * are known to hang the board; this issue is under investigation
  63. * (13 oct 05)
  64. */
  65. reg32 = OCCR_PCICOE1;
  66. #if 0
  67. /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
  68. reg32 = 0xff000000;
  69. #endif
  70. if (clk->spmr & SPMR_CKID) {
  71. /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
  72. * fields accordingly */
  73. reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
  74. reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
  75. | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
  76. | OCCR_PCICD6 | OCCR_PCICD7);
  77. }
  78. clk->occr = reg32;
  79. udelay(2000);
  80. /* Configure PCI Local Access Windows */
  81. pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  82. pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
  83. pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  84. pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
  85. udelay(2000);
  86. mpc83xx_pci_init(1, reg);
  87. }