pf0100_otp.inc 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014-2016, Toradex AG
  4. */
  5. // Register Output for PF0100 programmer
  6. // Customer: Toradex AG
  7. // Program: Apalis iMX6
  8. // Sample marking:
  9. // Date: 12.02.2014
  10. // Time: 17:16:41
  11. // Generated from Spreadsheet Revision: P1.8
  12. /* sed commands to get from programmer script to struct */
  13. /* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
  14. sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
  15. sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
  16. enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
  17. struct pmic_otp_prog_t{
  18. unsigned char cmd;
  19. unsigned char reg;
  20. unsigned short value;
  21. };
  22. struct pmic_otp_prog_t pmic_otp_prog[] = {
  23. {pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
  24. {pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
  25. {pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
  26. {pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
  27. {pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
  28. {pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
  29. {pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
  30. {pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
  31. {pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
  32. {pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
  33. {pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
  34. {pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
  35. {pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
  36. {pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
  37. {pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
  38. {pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
  39. {pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
  40. {pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
  41. {pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
  42. {pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
  43. {pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
  44. {pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
  45. {pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
  46. {pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
  47. {pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
  48. {pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
  49. {pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
  50. {pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
  51. {pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
  52. {pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
  53. {pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
  54. {pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
  55. #if 0 /* TBB mode */
  56. {pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
  57. {pmic_delay, 0, 10},
  58. #else
  59. // Write OTP
  60. {pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
  61. {pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
  62. {pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
  63. {pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
  64. {pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
  65. {pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
  66. {pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
  67. {pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
  68. //-----------------------------------------------------------------------------------
  69. {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  70. {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  71. {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  72. {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  73. {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  74. {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  75. {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  76. {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  77. {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  78. {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  79. //-----------------------------------------------------------------------------------
  80. {pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
  81. //VPGM:DOWN:n
  82. //VPGM:UP:n
  83. {pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
  84. //-----------------------------------------------------------------------------------
  85. // PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
  86. //-----------------------------------------------------------------------------------
  87. // BANK 1
  88. //-----------------------------------------------------------------------------------
  89. {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  90. {pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  91. {pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
  92. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  93. {pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
  94. {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  95. //-----------------------------------------------------------------------------------
  96. // BANK 2
  97. //-----------------------------------------------------------------------------------
  98. {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  99. {pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  100. {pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
  101. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  102. {pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
  103. {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  104. //-----------------------------------------------------------------------------------
  105. // BANK 3
  106. //-----------------------------------------------------------------------------------
  107. {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  108. {pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  109. {pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
  110. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  111. {pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
  112. {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  113. //-----------------------------------------------------------------------------------
  114. // BANK 4
  115. //-----------------------------------------------------------------------------------
  116. {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  117. {pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  118. {pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
  119. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  120. {pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
  121. {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  122. //-----------------------------------------------------------------------------------
  123. // BANK 5
  124. //-----------------------------------------------------------------------------------
  125. {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  126. {pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  127. {pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
  128. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  129. {pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
  130. {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  131. //-----------------------------------------------------------------------------------
  132. // BANK 6
  133. //-----------------------------------------------------------------------------------
  134. {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  135. {pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  136. {pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
  137. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  138. {pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
  139. {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  140. //-----------------------------------------------------------------------------------
  141. // BANK 7
  142. //-----------------------------------------------------------------------------------
  143. {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  144. {pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  145. {pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
  146. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  147. {pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
  148. {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  149. //-----------------------------------------------------------------------------------
  150. // BANK 8
  151. //-----------------------------------------------------------------------------------
  152. {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  153. {pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  154. {pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
  155. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  156. {pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
  157. {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  158. //-----------------------------------------------------------------------------------
  159. // BANK 9
  160. //-----------------------------------------------------------------------------------
  161. {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  162. {pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  163. {pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
  164. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  165. {pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
  166. {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  167. //-----------------------------------------------------------------------------------
  168. // BANK 10
  169. //-----------------------------------------------------------------------------------
  170. {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  171. {pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  172. {pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
  173. {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  174. {pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
  175. {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  176. //-----------------------------------------------------------------------------------
  177. {pmic_vpgm, 0, 0}, // Turn off 8V SWBST
  178. {pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
  179. {pmic_i2c, 0xD0, 0x00}, // Clear
  180. {pmic_i2c, 0xD1, 0x00}, // Clear
  181. {pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
  182. {pmic_delay, 0, 500},
  183. {pmic_pwr, 0, 1},
  184. #endif
  185. };