apalis_imx6.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. * Copyright (C) 2014-2019, Toradex AG
  6. * copied from nitrogen6x
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <ahci.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/mx6-ddr.h>
  16. #include <asm/arch/mx6-pins.h>
  17. #include <asm/arch/mxc_hdmi.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/bootm.h>
  20. #include <asm/gpio.h>
  21. #include <asm/mach-imx/boot_mode.h>
  22. #include <asm/mach-imx/iomux-v3.h>
  23. #include <asm/mach-imx/sata.h>
  24. #include <asm/mach-imx/video.h>
  25. #include <dm/device-internal.h>
  26. #include <dm/platform_data/serial_mxc.h>
  27. #include <dwc_ahsata.h>
  28. #include <env.h>
  29. #include <fsl_esdhc_imx.h>
  30. #include <imx_thermal.h>
  31. #include <micrel.h>
  32. #include <miiphy.h>
  33. #include <netdev.h>
  34. #include "../common/tdx-cfg-block.h"
  35. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  36. #include "pf0100.h"
  37. #endif
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  40. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  41. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  43. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
  44. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  45. #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  46. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  47. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  48. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  49. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  50. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  51. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  52. PAD_CTL_SRE_SLOW)
  53. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  54. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  55. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  56. #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  57. #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  58. #define APALIS_IMX6_SATA_INIT_RETRIES 10
  59. int dram_init(void)
  60. {
  61. /* use the DDR controllers configured size */
  62. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  63. (ulong)imx_ddr_size());
  64. return 0;
  65. }
  66. /* Apalis UART1 */
  67. iomux_v3_cfg_t const uart1_pads_dce[] = {
  68. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  70. };
  71. iomux_v3_cfg_t const uart1_pads_dte[] = {
  72. MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  73. MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  74. };
  75. #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  76. /* Apalis MMC1 */
  77. iomux_v3_cfg_t const usdhc1_pads[] = {
  78. MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80. MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81. MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82. MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83. MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84. MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85. MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86. MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87. MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88. MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  89. # define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
  90. };
  91. /* Apalis SD1 */
  92. iomux_v3_cfg_t const usdhc2_pads[] = {
  93. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  100. # define GPIO_SD_CD IMX_GPIO_NR(6, 14)
  101. };
  102. /* eMMC */
  103. iomux_v3_cfg_t const usdhc3_pads[] = {
  104. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  105. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  106. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  107. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  108. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  109. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  110. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  111. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  112. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  113. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  114. MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
  115. };
  116. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  117. int mx6_rgmii_rework(struct phy_device *phydev)
  118. {
  119. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  120. ksz9031_phy_extended_write(phydev, 0x02,
  121. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  122. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  123. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  124. ksz9031_phy_extended_write(phydev, 0x02,
  125. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  126. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  127. /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  128. ksz9031_phy_extended_write(phydev, 0x02,
  129. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  130. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  131. /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  132. ksz9031_phy_extended_write(phydev, 0x02,
  133. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  134. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  135. return 0;
  136. }
  137. iomux_v3_cfg_t const enet_pads[] = {
  138. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  139. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  140. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  141. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  142. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  143. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  144. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  145. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  146. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  147. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  148. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  149. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  150. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  151. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  152. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  153. /* KSZ9031 PHY Reset */
  154. MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  155. MUX_MODE_SION,
  156. # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
  157. };
  158. static void setup_iomux_enet(void)
  159. {
  160. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  161. }
  162. static int reset_enet_phy(struct mii_dev *bus)
  163. {
  164. /* Reset KSZ9031 PHY */
  165. gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
  166. gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
  167. mdelay(10);
  168. gpio_set_value(GPIO_ENET_PHY_RESET, 1);
  169. return 0;
  170. }
  171. /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
  172. iomux_v3_cfg_t const gpio_pads[] = {
  173. /* Apalis GPIO1 - GPIO8 */
  174. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  175. MUX_MODE_SION,
  176. MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
  177. MUX_MODE_SION,
  178. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  179. MUX_MODE_SION,
  180. MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
  181. MUX_MODE_SION,
  182. MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
  183. MUX_MODE_SION,
  184. MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
  185. MUX_MODE_SION,
  186. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
  187. MUX_MODE_SION,
  188. MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  189. MUX_MODE_SION,
  190. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  191. MUX_MODE_SION,
  192. };
  193. static void setup_iomux_gpio(void)
  194. {
  195. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  196. }
  197. iomux_v3_cfg_t const usb_pads[] = {
  198. /* USBH_EN */
  199. MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  200. # define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
  201. /* USB_VBUS_DET */
  202. MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  203. # define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
  204. /* USBO1_ID */
  205. MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
  206. /* USBO1_EN */
  207. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  208. # define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
  209. };
  210. /*
  211. * UARTs are used in DTE mode, switch the mode on all UARTs before
  212. * any pinmuxing connects a (DCE) output to a transceiver output.
  213. */
  214. #define UCR3 0x88 /* FIFO Control Register */
  215. #define UCR3_RI BIT(8) /* RIDELT DTE mode */
  216. #define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
  217. #define UFCR 0x90 /* FIFO Control Register */
  218. #define UFCR_DCEDTE BIT(6) /* DCE=0 */
  219. static void setup_dtemode_uart(void)
  220. {
  221. setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
  222. setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
  223. setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
  224. setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
  225. clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
  226. clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
  227. clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
  228. clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
  229. }
  230. static void setup_dcemode_uart(void)
  231. {
  232. clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
  233. clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
  234. clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
  235. clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
  236. }
  237. static void setup_iomux_dte_uart(void)
  238. {
  239. setup_dtemode_uart();
  240. imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
  241. ARRAY_SIZE(uart1_pads_dte));
  242. }
  243. static void setup_iomux_dce_uart(void)
  244. {
  245. setup_dcemode_uart();
  246. imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
  247. ARRAY_SIZE(uart1_pads_dce));
  248. }
  249. #ifdef CONFIG_USB_EHCI_MX6
  250. int board_ehci_hcd_init(int port)
  251. {
  252. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  253. return 0;
  254. }
  255. #endif
  256. #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  257. /* use the following sequence: eMMC, MMC1, SD1 */
  258. struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  259. {USDHC3_BASE_ADDR},
  260. {USDHC1_BASE_ADDR},
  261. {USDHC2_BASE_ADDR},
  262. };
  263. int board_mmc_getcd(struct mmc *mmc)
  264. {
  265. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  266. int ret = true; /* default: assume inserted */
  267. switch (cfg->esdhc_base) {
  268. case USDHC1_BASE_ADDR:
  269. gpio_request(GPIO_MMC_CD, "MMC_CD");
  270. gpio_direction_input(GPIO_MMC_CD);
  271. ret = !gpio_get_value(GPIO_MMC_CD);
  272. break;
  273. case USDHC2_BASE_ADDR:
  274. gpio_request(GPIO_MMC_CD, "SD_CD");
  275. gpio_direction_input(GPIO_SD_CD);
  276. ret = !gpio_get_value(GPIO_SD_CD);
  277. break;
  278. }
  279. return ret;
  280. }
  281. int board_mmc_init(bd_t *bis)
  282. {
  283. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  284. unsigned reg = readl(&psrc->sbmr1) >> 11;
  285. /*
  286. * Upon reading BOOT_CFG register the following map is done:
  287. * Bit 11 and 12 of BOOT_CFG register can determine the current
  288. * mmc port
  289. * 0x1 SD1
  290. * 0x2 SD2
  291. * 0x3 SD4
  292. */
  293. switch (reg & 0x3) {
  294. case 0x0:
  295. imx_iomux_v3_setup_multiple_pads(
  296. usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  297. usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
  298. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  299. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  300. break;
  301. case 0x1:
  302. imx_iomux_v3_setup_multiple_pads(
  303. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  304. usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  305. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  306. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  307. break;
  308. case 0x2:
  309. imx_iomux_v3_setup_multiple_pads(
  310. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  311. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  312. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  313. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  314. break;
  315. default:
  316. puts("MMC boot device not available");
  317. }
  318. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  319. }
  320. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  321. int board_phy_config(struct phy_device *phydev)
  322. {
  323. mx6_rgmii_rework(phydev);
  324. if (phydev->drv->config)
  325. phydev->drv->config(phydev);
  326. return 0;
  327. }
  328. int board_eth_init(bd_t *bis)
  329. {
  330. uint32_t base = IMX_FEC_BASE;
  331. struct mii_dev *bus = NULL;
  332. struct phy_device *phydev = NULL;
  333. int ret;
  334. setup_iomux_enet();
  335. #ifdef CONFIG_FEC_MXC
  336. bus = fec_get_miibus(base, -1);
  337. if (!bus)
  338. return 0;
  339. bus->reset = reset_enet_phy;
  340. /* scan PHY 4,5,6,7 */
  341. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  342. if (!phydev) {
  343. free(bus);
  344. puts("no PHY found\n");
  345. return 0;
  346. }
  347. printf("using PHY at %d\n", phydev->addr);
  348. ret = fec_probe(bis, -1, base, bus, phydev);
  349. if (ret) {
  350. printf("FEC MXC: %s:failed\n", __func__);
  351. free(phydev);
  352. free(bus);
  353. }
  354. #endif /* CONFIG_FEC_MXC */
  355. return 0;
  356. }
  357. static iomux_v3_cfg_t const pwr_intb_pads[] = {
  358. /*
  359. * the bootrom sets the iomux to vselect, potentially connecting
  360. * two outputs. Set this back to GPIO
  361. */
  362. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
  363. };
  364. #if defined(CONFIG_VIDEO_IPUV3)
  365. static iomux_v3_cfg_t const backlight_pads[] = {
  366. /* Backlight on RGB connector: J15 */
  367. MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  368. MUX_MODE_SION,
  369. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
  370. /* additional CPU pin on BKL_PWM, keep in tristate */
  371. MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
  372. /* Backlight PWM, used as GPIO in U-Boot */
  373. MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  374. MUX_MODE_SION,
  375. #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
  376. /* buffer output enable 0: buffer enabled */
  377. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
  378. #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
  379. /* PSAVE# integrated VDAC */
  380. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  381. MUX_MODE_SION,
  382. #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
  383. };
  384. static iomux_v3_cfg_t const rgb_pads[] = {
  385. MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
  386. MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
  387. MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
  388. MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
  389. MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
  390. MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
  391. MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
  392. MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
  393. MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
  394. MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
  395. MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
  396. MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
  397. MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
  398. MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
  399. MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
  400. MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
  401. MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
  402. MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
  403. MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
  404. MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
  405. MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
  406. MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
  407. MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
  408. MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
  409. MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
  410. MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
  411. MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
  412. MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
  413. };
  414. static void do_enable_hdmi(struct display_info_t const *dev)
  415. {
  416. imx_enable_hdmi_phy();
  417. }
  418. static void enable_lvds(struct display_info_t const *dev)
  419. {
  420. struct iomuxc *iomux = (struct iomuxc *)
  421. IOMUXC_BASE_ADDR;
  422. u32 reg = readl(&iomux->gpr[2]);
  423. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  424. writel(reg, &iomux->gpr[2]);
  425. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  426. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  427. gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
  428. }
  429. static void enable_rgb(struct display_info_t const *dev)
  430. {
  431. imx_iomux_v3_setup_multiple_pads(
  432. rgb_pads,
  433. ARRAY_SIZE(rgb_pads));
  434. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  435. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  436. gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
  437. }
  438. static int detect_default(struct display_info_t const *dev)
  439. {
  440. (void) dev;
  441. return 1;
  442. }
  443. struct display_info_t const displays[] = {{
  444. .bus = -1,
  445. .addr = 0,
  446. .pixfmt = IPU_PIX_FMT_RGB24,
  447. .detect = detect_hdmi,
  448. .enable = do_enable_hdmi,
  449. .mode = {
  450. .name = "HDMI",
  451. .refresh = 60,
  452. .xres = 1024,
  453. .yres = 768,
  454. .pixclock = 15385,
  455. .left_margin = 220,
  456. .right_margin = 40,
  457. .upper_margin = 21,
  458. .lower_margin = 7,
  459. .hsync_len = 60,
  460. .vsync_len = 10,
  461. .sync = FB_SYNC_EXT,
  462. .vmode = FB_VMODE_NONINTERLACED
  463. } }, {
  464. .bus = -1,
  465. .addr = 0,
  466. .di = 1,
  467. .pixfmt = IPU_PIX_FMT_RGB24,
  468. .detect = detect_default,
  469. .enable = enable_rgb,
  470. .mode = {
  471. .name = "vga-rgb",
  472. .refresh = 60,
  473. .xres = 640,
  474. .yres = 480,
  475. .pixclock = 33000,
  476. .left_margin = 48,
  477. .right_margin = 16,
  478. .upper_margin = 31,
  479. .lower_margin = 11,
  480. .hsync_len = 96,
  481. .vsync_len = 2,
  482. .sync = 0,
  483. .vmode = FB_VMODE_NONINTERLACED
  484. } }, {
  485. .bus = -1,
  486. .addr = 0,
  487. .di = 1,
  488. .pixfmt = IPU_PIX_FMT_RGB24,
  489. .enable = enable_rgb,
  490. .mode = {
  491. .name = "wvga-rgb",
  492. .refresh = 60,
  493. .xres = 800,
  494. .yres = 480,
  495. .pixclock = 25000,
  496. .left_margin = 40,
  497. .right_margin = 88,
  498. .upper_margin = 33,
  499. .lower_margin = 10,
  500. .hsync_len = 128,
  501. .vsync_len = 2,
  502. .sync = 0,
  503. .vmode = FB_VMODE_NONINTERLACED
  504. } }, {
  505. .bus = -1,
  506. .addr = 0,
  507. .pixfmt = IPU_PIX_FMT_LVDS666,
  508. .enable = enable_lvds,
  509. .mode = {
  510. .name = "wsvga-lvds",
  511. .refresh = 60,
  512. .xres = 1024,
  513. .yres = 600,
  514. .pixclock = 15385,
  515. .left_margin = 220,
  516. .right_margin = 40,
  517. .upper_margin = 21,
  518. .lower_margin = 7,
  519. .hsync_len = 60,
  520. .vsync_len = 10,
  521. .sync = FB_SYNC_EXT,
  522. .vmode = FB_VMODE_NONINTERLACED
  523. } } };
  524. size_t display_count = ARRAY_SIZE(displays);
  525. static void setup_display(void)
  526. {
  527. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  528. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  529. int reg;
  530. enable_ipu_clock();
  531. imx_setup_hdmi();
  532. /* Turn on LDB0,IPU,IPU DI0 clocks */
  533. reg = __raw_readl(&mxc_ccm->CCGR3);
  534. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  535. writel(reg, &mxc_ccm->CCGR3);
  536. /* set LDB0, LDB1 clk select to 011/011 */
  537. reg = readl(&mxc_ccm->cs2cdr);
  538. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  539. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  540. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  541. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  542. writel(reg, &mxc_ccm->cs2cdr);
  543. reg = readl(&mxc_ccm->cscmr2);
  544. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  545. writel(reg, &mxc_ccm->cscmr2);
  546. reg = readl(&mxc_ccm->chsccdr);
  547. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  548. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  549. writel(reg, &mxc_ccm->chsccdr);
  550. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  551. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  552. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  553. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  554. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  555. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  556. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  557. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  558. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  559. writel(reg, &iomux->gpr[2]);
  560. reg = readl(&iomux->gpr[3]);
  561. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  562. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  563. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  564. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  565. writel(reg, &iomux->gpr[3]);
  566. /* backlight unconditionally on for now */
  567. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  568. ARRAY_SIZE(backlight_pads));
  569. /* use 0 for EDT 7", use 1 for LG fullHD panel */
  570. gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
  571. gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
  572. gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
  573. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  574. gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
  575. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  576. }
  577. /*
  578. * Backlight off before OS handover
  579. */
  580. void board_preboot_os(void)
  581. {
  582. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
  583. gpio_direction_output(RGB_BACKLIGHT_GP, 0);
  584. }
  585. #endif /* defined(CONFIG_VIDEO_IPUV3) */
  586. int board_early_init_f(void)
  587. {
  588. imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
  589. ARRAY_SIZE(pwr_intb_pads));
  590. #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
  591. setup_iomux_dte_uart();
  592. #else
  593. setup_iomux_dce_uart();
  594. #endif
  595. return 0;
  596. }
  597. /*
  598. * Do not overwrite the console
  599. * Use always serial for U-Boot console
  600. */
  601. int overwrite_console(void)
  602. {
  603. return 1;
  604. }
  605. int board_init(void)
  606. {
  607. /* address of boot parameters */
  608. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  609. #if defined(CONFIG_VIDEO_IPUV3)
  610. setup_display();
  611. #endif
  612. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  613. (void) pmic_init();
  614. #endif
  615. #ifdef CONFIG_SATA
  616. setup_sata();
  617. #endif
  618. setup_iomux_gpio();
  619. return 0;
  620. }
  621. #ifdef CONFIG_BOARD_LATE_INIT
  622. int board_late_init(void)
  623. {
  624. #if defined(CONFIG_REVISION_TAG) && \
  625. defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
  626. char env_str[256];
  627. u32 rev;
  628. rev = get_board_rev();
  629. snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
  630. env_set("board_rev", env_str);
  631. #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
  632. if ((rev & 0xfff0) == 0x0100) {
  633. char *fdt_env;
  634. /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
  635. setup_iomux_dce_uart();
  636. /* if using the default device tree, use version for V1.0 HW */
  637. fdt_env = env_get("fdt_file");
  638. if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
  639. env_set("fdt_file", FDT_FILE_V1_0);
  640. printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
  641. #ifndef CONFIG_ENV_IS_NOWHERE
  642. env_save();
  643. #endif
  644. }
  645. }
  646. #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
  647. #endif /* CONFIG_REVISION_TAG */
  648. #ifdef CONFIG_CMD_USB_SDP
  649. if (is_boot_from_usb()) {
  650. printf("Serial Downloader recovery mode, using sdp command\n");
  651. env_set("bootdelay", "0");
  652. env_set("bootcmd", "sdp 0");
  653. }
  654. #endif /* CONFIG_CMD_USB_SDP */
  655. return 0;
  656. }
  657. #endif /* CONFIG_BOARD_LATE_INIT */
  658. int checkboard(void)
  659. {
  660. char it[] = " IT";
  661. int minc, maxc;
  662. switch (get_cpu_temp_grade(&minc, &maxc)) {
  663. case TEMP_AUTOMOTIVE:
  664. case TEMP_INDUSTRIAL:
  665. break;
  666. case TEMP_EXTCOMMERCIAL:
  667. default:
  668. it[0] = 0;
  669. };
  670. printf("Model: Toradex Apalis iMX6 %s %s%s\n",
  671. is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
  672. (gd->ram_size == 0x80000000) ? "2GB" :
  673. (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
  674. return 0;
  675. }
  676. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  677. int ft_board_setup(void *blob, bd_t *bd)
  678. {
  679. return ft_common_board_setup(blob, bd);
  680. }
  681. #endif
  682. #ifdef CONFIG_CMD_BMODE
  683. static const struct boot_mode board_boot_modes[] = {
  684. /* 4-bit bus width */
  685. {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  686. {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  687. {NULL, 0},
  688. };
  689. #endif
  690. int misc_init_r(void)
  691. {
  692. #ifdef CONFIG_CMD_BMODE
  693. add_board_boot_modes(board_boot_modes);
  694. #endif
  695. return 0;
  696. }
  697. #ifdef CONFIG_LDO_BYPASS_CHECK
  698. /* TODO, use external pmic, for now always ldo_enable */
  699. void ldo_mode_set(int ldo_bypass)
  700. {
  701. return;
  702. }
  703. #endif
  704. #ifdef CONFIG_SPL_BUILD
  705. #include <spl.h>
  706. #include <linux/libfdt.h>
  707. #include "asm/arch/mx6q-ddr.h"
  708. #include "asm/arch/iomux.h"
  709. #include "asm/arch/crm_regs.h"
  710. static int mx6_com_dcd_table[] = {
  711. /* ddr-setup.cfg */
  712. MX6_IOM_DRAM_SDQS0, 0x00000030,
  713. MX6_IOM_DRAM_SDQS1, 0x00000030,
  714. MX6_IOM_DRAM_SDQS2, 0x00000030,
  715. MX6_IOM_DRAM_SDQS3, 0x00000030,
  716. MX6_IOM_DRAM_SDQS4, 0x00000030,
  717. MX6_IOM_DRAM_SDQS5, 0x00000030,
  718. MX6_IOM_DRAM_SDQS6, 0x00000030,
  719. MX6_IOM_DRAM_SDQS7, 0x00000030,
  720. MX6_IOM_GRP_B0DS, 0x00000030,
  721. MX6_IOM_GRP_B1DS, 0x00000030,
  722. MX6_IOM_GRP_B2DS, 0x00000030,
  723. MX6_IOM_GRP_B3DS, 0x00000030,
  724. MX6_IOM_GRP_B4DS, 0x00000030,
  725. MX6_IOM_GRP_B5DS, 0x00000030,
  726. MX6_IOM_GRP_B6DS, 0x00000030,
  727. MX6_IOM_GRP_B7DS, 0x00000030,
  728. MX6_IOM_GRP_ADDDS, 0x00000030,
  729. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  730. MX6_IOM_GRP_CTLDS, 0x00000030,
  731. MX6_IOM_DRAM_DQM0, 0x00020030,
  732. MX6_IOM_DRAM_DQM1, 0x00020030,
  733. MX6_IOM_DRAM_DQM2, 0x00020030,
  734. MX6_IOM_DRAM_DQM3, 0x00020030,
  735. MX6_IOM_DRAM_DQM4, 0x00020030,
  736. MX6_IOM_DRAM_DQM5, 0x00020030,
  737. MX6_IOM_DRAM_DQM6, 0x00020030,
  738. MX6_IOM_DRAM_DQM7, 0x00020030,
  739. MX6_IOM_DRAM_CAS, 0x00020030,
  740. MX6_IOM_DRAM_RAS, 0x00020030,
  741. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  742. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  743. MX6_IOM_DRAM_RESET, 0x00020030,
  744. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  745. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  746. MX6_IOM_DRAM_SDODT0, 0x00003030,
  747. MX6_IOM_DRAM_SDODT1, 0x00003030,
  748. /* (differential input) */
  749. MX6_IOM_DDRMODE_CTL, 0x00020000,
  750. /* (differential input) */
  751. MX6_IOM_GRP_DDRMODE, 0x00020000,
  752. /* disable ddr pullups */
  753. MX6_IOM_GRP_DDRPKE, 0x00000000,
  754. MX6_IOM_DRAM_SDBA2, 0x00000000,
  755. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  756. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  757. /* Read data DQ Byte0-3 delay */
  758. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  759. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  760. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  761. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  762. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  763. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  764. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  765. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  766. /*
  767. * MDMISC mirroring interleaved (row/bank/col)
  768. */
  769. MX6_MMDC_P0_MDMISC, 0x00081740,
  770. /*
  771. * MDSCR con_req
  772. */
  773. MX6_MMDC_P0_MDSCR, 0x00008000,
  774. /* 1066mhz_4x128mx16.cfg */
  775. MX6_MMDC_P0_MDPDC, 0x00020036,
  776. MX6_MMDC_P0_MDCFG0, 0x555A7954,
  777. MX6_MMDC_P0_MDCFG1, 0xDB328F64,
  778. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  779. MX6_MMDC_P0_MDRWD, 0x000026D2,
  780. MX6_MMDC_P0_MDOR, 0x005A1023,
  781. MX6_MMDC_P0_MDOTC, 0x09555050,
  782. MX6_MMDC_P0_MDPDC, 0x00025576,
  783. MX6_MMDC_P0_MDASP, 0x00000027,
  784. MX6_MMDC_P0_MDCTL, 0x831A0000,
  785. MX6_MMDC_P0_MDSCR, 0x04088032,
  786. MX6_MMDC_P0_MDSCR, 0x00008033,
  787. MX6_MMDC_P0_MDSCR, 0x00428031,
  788. MX6_MMDC_P0_MDSCR, 0x19308030,
  789. MX6_MMDC_P0_MDSCR, 0x04008040,
  790. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  791. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  792. MX6_MMDC_P0_MDREF, 0x00005800,
  793. MX6_MMDC_P0_MPODTCTRL, 0x00000000,
  794. MX6_MMDC_P1_MPODTCTRL, 0x00000000,
  795. MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
  796. MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
  797. MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
  798. MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
  799. MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
  800. MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
  801. MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
  802. MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
  803. MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
  804. MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
  805. MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
  806. MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
  807. MX6_MMDC_P0_MPMUR0, 0x00000800,
  808. MX6_MMDC_P1_MPMUR0, 0x00000800,
  809. MX6_MMDC_P0_MDSCR, 0x00000000,
  810. MX6_MMDC_P0_MAPSR, 0x00011006,
  811. };
  812. static int mx6_it_dcd_table[] = {
  813. /* ddr-setup.cfg */
  814. MX6_IOM_DRAM_SDQS0, 0x00000030,
  815. MX6_IOM_DRAM_SDQS1, 0x00000030,
  816. MX6_IOM_DRAM_SDQS2, 0x00000030,
  817. MX6_IOM_DRAM_SDQS3, 0x00000030,
  818. MX6_IOM_DRAM_SDQS4, 0x00000030,
  819. MX6_IOM_DRAM_SDQS5, 0x00000030,
  820. MX6_IOM_DRAM_SDQS6, 0x00000030,
  821. MX6_IOM_DRAM_SDQS7, 0x00000030,
  822. MX6_IOM_GRP_B0DS, 0x00000030,
  823. MX6_IOM_GRP_B1DS, 0x00000030,
  824. MX6_IOM_GRP_B2DS, 0x00000030,
  825. MX6_IOM_GRP_B3DS, 0x00000030,
  826. MX6_IOM_GRP_B4DS, 0x00000030,
  827. MX6_IOM_GRP_B5DS, 0x00000030,
  828. MX6_IOM_GRP_B6DS, 0x00000030,
  829. MX6_IOM_GRP_B7DS, 0x00000030,
  830. MX6_IOM_GRP_ADDDS, 0x00000030,
  831. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  832. MX6_IOM_GRP_CTLDS, 0x00000030,
  833. MX6_IOM_DRAM_DQM0, 0x00020030,
  834. MX6_IOM_DRAM_DQM1, 0x00020030,
  835. MX6_IOM_DRAM_DQM2, 0x00020030,
  836. MX6_IOM_DRAM_DQM3, 0x00020030,
  837. MX6_IOM_DRAM_DQM4, 0x00020030,
  838. MX6_IOM_DRAM_DQM5, 0x00020030,
  839. MX6_IOM_DRAM_DQM6, 0x00020030,
  840. MX6_IOM_DRAM_DQM7, 0x00020030,
  841. MX6_IOM_DRAM_CAS, 0x00020030,
  842. MX6_IOM_DRAM_RAS, 0x00020030,
  843. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  844. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  845. MX6_IOM_DRAM_RESET, 0x00020030,
  846. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  847. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  848. MX6_IOM_DRAM_SDODT0, 0x00003030,
  849. MX6_IOM_DRAM_SDODT1, 0x00003030,
  850. /* (differential input) */
  851. MX6_IOM_DDRMODE_CTL, 0x00020000,
  852. /* (differential input) */
  853. MX6_IOM_GRP_DDRMODE, 0x00020000,
  854. /* disable ddr pullups */
  855. MX6_IOM_GRP_DDRPKE, 0x00000000,
  856. MX6_IOM_DRAM_SDBA2, 0x00000000,
  857. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  858. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  859. /* Read data DQ Byte0-3 delay */
  860. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  861. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  862. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  863. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  864. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  865. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  866. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  867. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  868. /*
  869. * MDMISC mirroring interleaved (row/bank/col)
  870. */
  871. MX6_MMDC_P0_MDMISC, 0x00081740,
  872. /*
  873. * MDSCR con_req
  874. */
  875. MX6_MMDC_P0_MDSCR, 0x00008000,
  876. /* 1066mhz_4x256mx16.cfg */
  877. MX6_MMDC_P0_MDPDC, 0x00020036,
  878. MX6_MMDC_P0_MDCFG0, 0x898E78f5,
  879. MX6_MMDC_P0_MDCFG1, 0xff328f64,
  880. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  881. MX6_MMDC_P0_MDRWD, 0x000026D2,
  882. MX6_MMDC_P0_MDOR, 0x008E1023,
  883. MX6_MMDC_P0_MDOTC, 0x09444040,
  884. MX6_MMDC_P0_MDPDC, 0x00025576,
  885. MX6_MMDC_P0_MDASP, 0x00000047,
  886. MX6_MMDC_P0_MDCTL, 0x841A0000,
  887. MX6_MMDC_P0_MDSCR, 0x02888032,
  888. MX6_MMDC_P0_MDSCR, 0x00008033,
  889. MX6_MMDC_P0_MDSCR, 0x00048031,
  890. MX6_MMDC_P0_MDSCR, 0x19408030,
  891. MX6_MMDC_P0_MDSCR, 0x04008040,
  892. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  893. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  894. MX6_MMDC_P0_MDREF, 0x00007800,
  895. MX6_MMDC_P0_MPODTCTRL, 0x00022227,
  896. MX6_MMDC_P1_MPODTCTRL, 0x00022227,
  897. MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
  898. MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
  899. MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
  900. MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
  901. MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
  902. MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
  903. MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
  904. MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
  905. MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
  906. MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
  907. MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
  908. MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
  909. MX6_MMDC_P0_MPMUR0, 0x00000800,
  910. MX6_MMDC_P1_MPMUR0, 0x00000800,
  911. MX6_MMDC_P0_MDSCR, 0x00000000,
  912. MX6_MMDC_P0_MAPSR, 0x00011006,
  913. };
  914. static void ccgr_init(void)
  915. {
  916. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  917. writel(0x00C03F3F, &ccm->CCGR0);
  918. writel(0x0030FC03, &ccm->CCGR1);
  919. writel(0x0FFFFFF3, &ccm->CCGR2);
  920. writel(0x3FF0300F, &ccm->CCGR3);
  921. writel(0x00FFF300, &ccm->CCGR4);
  922. writel(0x0F0000F3, &ccm->CCGR5);
  923. writel(0x000003FF, &ccm->CCGR6);
  924. /*
  925. * Setup CCM_CCOSR register as follows:
  926. *
  927. * cko1_en = 1 --> CKO1 enabled
  928. * cko1_div = 111 --> divide by 8
  929. * cko1_sel = 1011 --> ahb_clk_root
  930. *
  931. * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  932. */
  933. writel(0x000000FB, &ccm->ccosr);
  934. }
  935. static void ddr_init(int *table, int size)
  936. {
  937. int i;
  938. for (i = 0; i < size / 2 ; i++)
  939. writel(table[2 * i + 1], table[2 * i]);
  940. }
  941. static void spl_dram_init(void)
  942. {
  943. int minc, maxc;
  944. switch (get_cpu_temp_grade(&minc, &maxc)) {
  945. case TEMP_COMMERCIAL:
  946. case TEMP_EXTCOMMERCIAL:
  947. puts("Commercial temperature grade DDR3 timings.\n");
  948. ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
  949. break;
  950. case TEMP_INDUSTRIAL:
  951. case TEMP_AUTOMOTIVE:
  952. default:
  953. puts("Industrial temperature grade DDR3 timings.\n");
  954. ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
  955. break;
  956. };
  957. udelay(100);
  958. }
  959. void board_init_f(ulong dummy)
  960. {
  961. /* setup AIPS and disable watchdog */
  962. arch_cpu_init();
  963. ccgr_init();
  964. gpr_init();
  965. /* iomux */
  966. board_early_init_f();
  967. /* setup GP timer */
  968. timer_init();
  969. /* UART clocks enabled and gd valid - init serial console */
  970. preloader_console_init();
  971. #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
  972. /* Make sure we use dte mode */
  973. setup_dtemode_uart();
  974. #endif
  975. /* DDR initialization */
  976. spl_dram_init();
  977. /* Clear the BSS. */
  978. memset(__bss_start, 0, __bss_end - __bss_start);
  979. /* load/boot image from boot device */
  980. board_init_r(NULL, 0);
  981. }
  982. #ifdef CONFIG_SPL_LOAD_FIT
  983. int board_fit_config_name_match(const char *name)
  984. {
  985. if (!strcmp(name, "imx6-apalis"))
  986. return 0;
  987. return -1;
  988. }
  989. #endif
  990. void reset_cpu(ulong addr)
  991. {
  992. }
  993. #endif /* CONFIG_SPL_BUILD */
  994. static struct mxc_serial_platdata mxc_serial_plat = {
  995. .reg = (struct mxc_uart *)UART1_BASE,
  996. .use_dte = true,
  997. };
  998. U_BOOT_DEVICE(mxc_serial) = {
  999. .name = "serial_mxc",
  1000. .platdata = &mxc_serial_plat,
  1001. };