evm.c 33 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Texas Instruments Incorporated, <www.ti.com>
  5. *
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. *
  8. * Based on previous work by:
  9. * Aneesh V <aneesh@ti.com>
  10. * Steve Sakoman <steve@sakoman.com>
  11. */
  12. #include <common.h>
  13. #include <env.h>
  14. #include <init.h>
  15. #include <palmas.h>
  16. #include <sata.h>
  17. #include <serial.h>
  18. #include <linux/string.h>
  19. #include <asm/gpio.h>
  20. #include <usb.h>
  21. #include <linux/usb/gadget.h>
  22. #include <asm/omap_common.h>
  23. #include <asm/omap_sec_common.h>
  24. #include <asm/arch/gpio.h>
  25. #include <asm/arch/dra7xx_iodelay.h>
  26. #include <asm/emif.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <asm/arch/mmc_host_def.h>
  29. #include <asm/arch/sata.h>
  30. #include <dwc3-uboot.h>
  31. #include <dwc3-omap-uboot.h>
  32. #include <i2c.h>
  33. #include <ti-usb-phy-uboot.h>
  34. #include <miiphy.h>
  35. #include "mux_data.h"
  36. #include "../common/board_detect.h"
  37. #define board_is_dra76x_evm() board_ti_is("DRA76/7x")
  38. #define board_is_dra74x_evm() board_ti_is("5777xCPU")
  39. #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
  40. #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
  41. #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
  42. (strncmp("H", board_ti_get_rev(), 1) <= 0))
  43. #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
  44. (strncmp("C", board_ti_get_rev(), 1) <= 0))
  45. #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
  46. board_ti_get_emif2_size()
  47. #ifdef CONFIG_DRIVER_TI_CPSW
  48. #include <cpsw.h>
  49. #endif
  50. DECLARE_GLOBAL_DATA_PTR;
  51. /* GPIO 7_11 */
  52. #define GPIO_DDR_VTT_EN 203
  53. #define SYSINFO_BOARD_NAME_MAX_LEN 37
  54. /* I2C I/O Expander */
  55. #define NAND_PCF8575_ADDR 0x21
  56. #define NAND_PCF8575_I2C_BUS_NUM 0
  57. const struct omap_sysinfo sysinfo = {
  58. "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  59. };
  60. static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  61. .sdram_config_init = 0x61851ab2,
  62. .sdram_config = 0x61851ab2,
  63. .sdram_config2 = 0x08000000,
  64. .ref_ctrl = 0x000040F1,
  65. .ref_ctrl_final = 0x00001035,
  66. .sdram_tim1 = 0xCCCF36B3,
  67. .sdram_tim2 = 0x308F7FDA,
  68. .sdram_tim3 = 0x427F88A8,
  69. .read_idle_ctrl = 0x00050000,
  70. .zq_config = 0x0007190B,
  71. .temp_alert_config = 0x00000000,
  72. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  73. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  74. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  75. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  76. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  77. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  78. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  79. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  80. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  81. .emif_rd_wr_lvl_ctl = 0x00000000,
  82. .emif_rd_wr_exec_thresh = 0x00000305
  83. };
  84. static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  85. .sdram_config_init = 0x61851B32,
  86. .sdram_config = 0x61851B32,
  87. .sdram_config2 = 0x08000000,
  88. .ref_ctrl = 0x000040F1,
  89. .ref_ctrl_final = 0x00001035,
  90. .sdram_tim1 = 0xCCCF36B3,
  91. .sdram_tim2 = 0x308F7FDA,
  92. .sdram_tim3 = 0x427F88A8,
  93. .read_idle_ctrl = 0x00050000,
  94. .zq_config = 0x0007190B,
  95. .temp_alert_config = 0x00000000,
  96. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  97. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  98. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  99. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  100. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  101. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  102. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  103. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  104. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  105. .emif_rd_wr_lvl_ctl = 0x00000000,
  106. .emif_rd_wr_exec_thresh = 0x00000305
  107. };
  108. static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
  109. .sdram_config_init = 0x61862B32,
  110. .sdram_config = 0x61862B32,
  111. .sdram_config2 = 0x08000000,
  112. .ref_ctrl = 0x0000514C,
  113. .ref_ctrl_final = 0x0000144A,
  114. .sdram_tim1 = 0xD113781C,
  115. .sdram_tim2 = 0x30717FE3,
  116. .sdram_tim3 = 0x409F86A8,
  117. .read_idle_ctrl = 0x00050000,
  118. .zq_config = 0x5007190B,
  119. .temp_alert_config = 0x00000000,
  120. .emif_ddr_phy_ctlr_1_init = 0x0024400D,
  121. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  122. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  123. .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
  124. .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
  125. .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
  126. .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
  127. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  128. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  129. .emif_rd_wr_lvl_ctl = 0x00000000,
  130. .emif_rd_wr_exec_thresh = 0x00000305
  131. };
  132. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
  133. .sdram_config_init = 0x61862BB2,
  134. .sdram_config = 0x61862BB2,
  135. .sdram_config2 = 0x00000000,
  136. .ref_ctrl = 0x0000514D,
  137. .ref_ctrl_final = 0x0000144A,
  138. .sdram_tim1 = 0xD1137824,
  139. .sdram_tim2 = 0x30B37FE3,
  140. .sdram_tim3 = 0x409F8AD8,
  141. .read_idle_ctrl = 0x00050000,
  142. .zq_config = 0x5007190B,
  143. .temp_alert_config = 0x00000000,
  144. .emif_ddr_phy_ctlr_1_init = 0x0824400E,
  145. .emif_ddr_phy_ctlr_1 = 0x0E24400E,
  146. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  147. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  148. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  149. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  150. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  151. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  152. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  153. .emif_rd_wr_lvl_ctl = 0x00000000,
  154. .emif_rd_wr_exec_thresh = 0x00000305
  155. };
  156. const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
  157. .sdram_config_init = 0x61851ab2,
  158. .sdram_config = 0x61851ab2,
  159. .sdram_config2 = 0x08000000,
  160. .ref_ctrl = 0x000040F1,
  161. .ref_ctrl_final = 0x00001035,
  162. .sdram_tim1 = 0xCCCF36B3,
  163. .sdram_tim2 = 0x30BF7FDA,
  164. .sdram_tim3 = 0x427F8BA8,
  165. .read_idle_ctrl = 0x00050000,
  166. .zq_config = 0x0007190B,
  167. .temp_alert_config = 0x00000000,
  168. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  169. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  170. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  171. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  172. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  173. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  174. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  175. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  176. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  177. .emif_rd_wr_lvl_ctl = 0x00000000,
  178. .emif_rd_wr_exec_thresh = 0x00000305
  179. };
  180. const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
  181. .sdram_config_init = 0x61851B32,
  182. .sdram_config = 0x61851B32,
  183. .sdram_config2 = 0x08000000,
  184. .ref_ctrl = 0x000040F1,
  185. .ref_ctrl_final = 0x00001035,
  186. .sdram_tim1 = 0xCCCF36B3,
  187. .sdram_tim2 = 0x308F7FDA,
  188. .sdram_tim3 = 0x427F88A8,
  189. .read_idle_ctrl = 0x00050000,
  190. .zq_config = 0x0007190B,
  191. .temp_alert_config = 0x00000000,
  192. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  193. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  194. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  195. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  196. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  197. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  198. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  199. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  200. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  201. .emif_rd_wr_lvl_ctl = 0x00000000,
  202. .emif_rd_wr_exec_thresh = 0x00000305
  203. };
  204. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
  205. .sdram_config_init = 0x61862B32,
  206. .sdram_config = 0x61862B32,
  207. .sdram_config2 = 0x00000000,
  208. .ref_ctrl = 0x0000514C,
  209. .ref_ctrl_final = 0x0000144A,
  210. .sdram_tim1 = 0xD113783C,
  211. .sdram_tim2 = 0x30B47FE3,
  212. .sdram_tim3 = 0x409F8AD8,
  213. .read_idle_ctrl = 0x00050000,
  214. .zq_config = 0x5007190B,
  215. .temp_alert_config = 0x00000000,
  216. .emif_ddr_phy_ctlr_1_init = 0x0824400D,
  217. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  218. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  219. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  220. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  221. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  222. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  223. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  224. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  225. .emif_rd_wr_lvl_ctl = 0x00000000,
  226. .emif_rd_wr_exec_thresh = 0x00000305
  227. };
  228. const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
  229. .sdram_config_init = 0x61862B32,
  230. .sdram_config = 0x61862B32,
  231. .sdram_config2 = 0x00000000,
  232. .ref_ctrl = 0x0000514C,
  233. .ref_ctrl_final = 0x0000144A,
  234. .sdram_tim1 = 0xD113781C,
  235. .sdram_tim2 = 0x30B47FE3,
  236. .sdram_tim3 = 0x409F8AD8,
  237. .read_idle_ctrl = 0x00050000,
  238. .zq_config = 0x5007190B,
  239. .temp_alert_config = 0x00000000,
  240. .emif_ddr_phy_ctlr_1_init = 0x0824400D,
  241. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  242. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  243. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  244. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  245. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  246. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  247. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  248. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  249. .emif_rd_wr_lvl_ctl = 0x00000000,
  250. .emif_rd_wr_exec_thresh = 0x00000305
  251. };
  252. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  253. {
  254. u64 ram_size;
  255. ram_size = board_ti_get_emif_size();
  256. switch (omap_revision()) {
  257. case DRA752_ES1_0:
  258. case DRA752_ES1_1:
  259. case DRA752_ES2_0:
  260. switch (emif_nr) {
  261. case 1:
  262. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  263. *regs = &emif1_ddr3_532_mhz_1cs_2G;
  264. else
  265. *regs = &emif1_ddr3_532_mhz_1cs;
  266. break;
  267. case 2:
  268. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  269. *regs = &emif2_ddr3_532_mhz_1cs_2G;
  270. else
  271. *regs = &emif2_ddr3_532_mhz_1cs;
  272. break;
  273. }
  274. break;
  275. case DRA762_ABZ_ES1_0:
  276. case DRA762_ACD_ES1_0:
  277. case DRA762_ES1_0:
  278. if (emif_nr == 1)
  279. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
  280. else
  281. *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
  282. break;
  283. case DRA722_ES1_0:
  284. case DRA722_ES2_0:
  285. case DRA722_ES2_1:
  286. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  287. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
  288. else
  289. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
  290. break;
  291. default:
  292. *regs = &emif1_ddr3_532_mhz_1cs;
  293. }
  294. }
  295. static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
  296. .dmm_lisa_map_0 = 0x0,
  297. .dmm_lisa_map_1 = 0x80640300,
  298. .dmm_lisa_map_2 = 0xC0500220,
  299. .dmm_lisa_map_3 = 0xFF020100,
  300. .is_ma_present = 0x1
  301. };
  302. static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
  303. .dmm_lisa_map_0 = 0x0,
  304. .dmm_lisa_map_1 = 0x0,
  305. .dmm_lisa_map_2 = 0x80600100,
  306. .dmm_lisa_map_3 = 0xFF020100,
  307. .is_ma_present = 0x1
  308. };
  309. const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
  310. .dmm_lisa_map_0 = 0x0,
  311. .dmm_lisa_map_1 = 0x0,
  312. .dmm_lisa_map_2 = 0x80740300,
  313. .dmm_lisa_map_3 = 0xFF020100,
  314. .is_ma_present = 0x1
  315. };
  316. /*
  317. * DRA722 EVM EMIF1 2GB CONFIGURATION
  318. * EMIF1 4 devices of 512Mb x 8 Micron
  319. */
  320. const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
  321. .dmm_lisa_map_0 = 0x0,
  322. .dmm_lisa_map_1 = 0x0,
  323. .dmm_lisa_map_2 = 0x80700100,
  324. .dmm_lisa_map_3 = 0xFF020100,
  325. .is_ma_present = 0x1
  326. };
  327. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  328. {
  329. u64 ram_size;
  330. ram_size = board_ti_get_emif_size();
  331. switch (omap_revision()) {
  332. case DRA762_ABZ_ES1_0:
  333. case DRA762_ACD_ES1_0:
  334. case DRA762_ES1_0:
  335. case DRA752_ES1_0:
  336. case DRA752_ES1_1:
  337. case DRA752_ES2_0:
  338. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  339. *dmm_lisa_regs = &lisa_map_dra7_2GB;
  340. else
  341. *dmm_lisa_regs = &lisa_map_dra7_1536MB;
  342. break;
  343. case DRA722_ES1_0:
  344. case DRA722_ES2_0:
  345. case DRA722_ES2_1:
  346. default:
  347. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  348. *dmm_lisa_regs = &lisa_map_2G_x_2;
  349. else
  350. *dmm_lisa_regs = &lisa_map_2G_x_4;
  351. break;
  352. }
  353. }
  354. struct vcores_data dra752_volts = {
  355. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  356. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  357. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  358. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  359. .mpu.pmic = &tps659038,
  360. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  361. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  362. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  363. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  364. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  365. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  366. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  367. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  368. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  369. .eve.pmic = &tps659038,
  370. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  371. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  372. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  373. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  374. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  375. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  376. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  377. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  378. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  379. .gpu.pmic = &tps659038,
  380. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  381. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  382. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  383. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  384. .core.addr = TPS659038_REG_ADDR_SMPS7,
  385. .core.pmic = &tps659038,
  386. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  387. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  388. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  389. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  390. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  391. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  392. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  393. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  394. .iva.pmic = &tps659038,
  395. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  396. };
  397. struct vcores_data dra76x_volts = {
  398. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  399. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  400. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  401. .mpu.addr = LP87565_REG_ADDR_BUCK01,
  402. .mpu.pmic = &lp87565,
  403. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  404. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  405. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  406. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  407. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  408. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  409. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  410. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  411. .eve.addr = TPS65917_REG_ADDR_SMPS1,
  412. .eve.pmic = &tps659038,
  413. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  414. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  415. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  416. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  417. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  418. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  419. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  420. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  421. .gpu.addr = LP87565_REG_ADDR_BUCK23,
  422. .gpu.pmic = &lp87565,
  423. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  424. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  425. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  426. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  427. .core.addr = TPS65917_REG_ADDR_SMPS3,
  428. .core.pmic = &tps659038,
  429. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  430. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  431. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  432. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  433. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  434. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  435. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  436. .iva.addr = TPS65917_REG_ADDR_SMPS4,
  437. .iva.pmic = &tps659038,
  438. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  439. };
  440. struct vcores_data dra722_volts = {
  441. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  442. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  443. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  444. .mpu.addr = TPS65917_REG_ADDR_SMPS1,
  445. .mpu.pmic = &tps659038,
  446. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  447. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  448. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  449. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  450. .core.addr = TPS65917_REG_ADDR_SMPS2,
  451. .core.pmic = &tps659038,
  452. /*
  453. * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
  454. * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
  455. */
  456. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  457. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  458. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  459. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  460. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  461. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  462. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  463. .gpu.addr = TPS65917_REG_ADDR_SMPS3,
  464. .gpu.pmic = &tps659038,
  465. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  466. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  467. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  468. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  469. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  470. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  471. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  472. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  473. .eve.addr = TPS65917_REG_ADDR_SMPS3,
  474. .eve.pmic = &tps659038,
  475. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  476. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  477. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  478. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  479. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  480. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  481. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  482. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  483. .iva.addr = TPS65917_REG_ADDR_SMPS3,
  484. .iva.pmic = &tps659038,
  485. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  486. };
  487. struct vcores_data dra718_volts = {
  488. /*
  489. * In the case of dra71x GPU MPU and CORE
  490. * are all powered up by BUCK0 of LP873X PMIC
  491. */
  492. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  493. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  494. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  495. .mpu.addr = LP873X_REG_ADDR_BUCK0,
  496. .mpu.pmic = &lp8733,
  497. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  498. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  499. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  500. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  501. .core.addr = LP873X_REG_ADDR_BUCK0,
  502. .core.pmic = &lp8733,
  503. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  504. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  505. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  506. .gpu.addr = LP873X_REG_ADDR_BUCK0,
  507. .gpu.pmic = &lp8733,
  508. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  509. /*
  510. * The DSPEVE and IVA rails are grouped on DRA71x-evm
  511. * and are powered by BUCK1 of LP873X PMIC
  512. */
  513. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  514. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  515. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  516. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  517. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  518. .eve.addr = LP873X_REG_ADDR_BUCK1,
  519. .eve.pmic = &lp8733,
  520. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  521. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  522. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  523. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  524. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  525. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  526. .iva.addr = LP873X_REG_ADDR_BUCK1,
  527. .iva.pmic = &lp8733,
  528. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  529. };
  530. int get_voltrail_opp(int rail_offset)
  531. {
  532. int opp;
  533. switch (rail_offset) {
  534. case VOLT_MPU:
  535. opp = DRA7_MPU_OPP;
  536. /* DRA71x supports only OPP_NOM for MPU */
  537. if (board_is_dra71x_evm())
  538. opp = OPP_NOM;
  539. break;
  540. case VOLT_CORE:
  541. opp = DRA7_CORE_OPP;
  542. /* DRA71x supports only OPP_NOM for CORE */
  543. if (board_is_dra71x_evm())
  544. opp = OPP_NOM;
  545. break;
  546. case VOLT_GPU:
  547. opp = DRA7_GPU_OPP;
  548. /* DRA71x supports only OPP_NOM for GPU */
  549. if (board_is_dra71x_evm())
  550. opp = OPP_NOM;
  551. break;
  552. case VOLT_EVE:
  553. opp = DRA7_DSPEVE_OPP;
  554. /*
  555. * DRA71x does not support OPP_OD for EVE.
  556. * If OPP_OD is selected by menuconfig, fallback
  557. * to OPP_NOM.
  558. */
  559. if (board_is_dra71x_evm() && opp == OPP_OD)
  560. opp = OPP_NOM;
  561. break;
  562. case VOLT_IVA:
  563. opp = DRA7_IVA_OPP;
  564. /*
  565. * DRA71x does not support OPP_OD for IVA.
  566. * If OPP_OD is selected by menuconfig, fallback
  567. * to OPP_NOM.
  568. */
  569. if (board_is_dra71x_evm() && opp == OPP_OD)
  570. opp = OPP_NOM;
  571. break;
  572. default:
  573. opp = OPP_NOM;
  574. }
  575. return opp;
  576. }
  577. /**
  578. * @brief board_init
  579. *
  580. * @return 0
  581. */
  582. int board_init(void)
  583. {
  584. gpmc_init();
  585. gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  586. return 0;
  587. }
  588. int dram_init_banksize(void)
  589. {
  590. u64 ram_size;
  591. ram_size = board_ti_get_emif_size();
  592. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  593. gd->bd->bi_dram[0].size = get_effective_memsize();
  594. if (ram_size > CONFIG_MAX_MEM_MAPPED) {
  595. gd->bd->bi_dram[1].start = 0x200000000;
  596. gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
  597. }
  598. return 0;
  599. }
  600. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  601. static int device_okay(const char *path)
  602. {
  603. int node;
  604. node = fdt_path_offset(gd->fdt_blob, path);
  605. if (node < 0)
  606. return 0;
  607. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  608. }
  609. #endif
  610. int board_late_init(void)
  611. {
  612. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  613. char *name = "unknown";
  614. if (is_dra72x()) {
  615. if (board_is_dra72x_revc_or_later())
  616. name = "dra72x-revc";
  617. else if (board_is_dra71x_evm())
  618. name = "dra71x";
  619. else
  620. name = "dra72x";
  621. } else if (is_dra76x_abz()) {
  622. name = "dra76x_abz";
  623. } else if (is_dra76x_acd()) {
  624. name = "dra76x_acd";
  625. } else {
  626. name = "dra7xx";
  627. }
  628. set_board_info_env(name);
  629. /*
  630. * Default FIT boot on HS devices. Non FIT images are not allowed
  631. * on HS devices.
  632. */
  633. if (get_device_type() == HS_DEVICE)
  634. env_set("boot_fit", "1");
  635. omap_die_id_serial();
  636. omap_set_fastboot_vars();
  637. /*
  638. * Hook the LDO1 regulator to EN pin. This applies only to LP8733
  639. * Rest all regulators are hooked to EN Pin at reset.
  640. */
  641. if (board_is_dra71x_evm())
  642. palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
  643. #endif
  644. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  645. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  646. enable_usb_clocks(0);
  647. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  648. enable_usb_clocks(1);
  649. #endif
  650. return 0;
  651. }
  652. #ifdef CONFIG_SPL_BUILD
  653. void do_board_detect(void)
  654. {
  655. int rc;
  656. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  657. CONFIG_EEPROM_CHIP_ADDRESS);
  658. if (rc)
  659. printf("ti_i2c_eeprom_init failed %d\n", rc);
  660. }
  661. #else
  662. void do_board_detect(void)
  663. {
  664. char *bname = NULL;
  665. int rc;
  666. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  667. CONFIG_EEPROM_CHIP_ADDRESS);
  668. if (rc)
  669. printf("ti_i2c_eeprom_init failed %d\n", rc);
  670. if (board_is_dra74x_evm()) {
  671. bname = "DRA74x EVM";
  672. } else if (board_is_dra72x_evm()) {
  673. bname = "DRA72x EVM";
  674. } else if (board_is_dra71x_evm()) {
  675. bname = "DRA71x EVM";
  676. } else if (board_is_dra76x_evm()) {
  677. bname = "DRA76x EVM";
  678. } else {
  679. /* If EEPROM is not populated */
  680. if (is_dra72x())
  681. bname = "DRA72x EVM";
  682. else
  683. bname = "DRA74x EVM";
  684. }
  685. if (bname)
  686. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  687. "Board: %s REV %s\n", bname, board_ti_get_rev());
  688. }
  689. #endif /* CONFIG_SPL_BUILD */
  690. void vcores_init(void)
  691. {
  692. if (board_is_dra74x_evm()) {
  693. *omap_vcores = &dra752_volts;
  694. } else if (board_is_dra72x_evm()) {
  695. *omap_vcores = &dra722_volts;
  696. } else if (board_is_dra71x_evm()) {
  697. *omap_vcores = &dra718_volts;
  698. } else if (board_is_dra76x_evm()) {
  699. *omap_vcores = &dra76x_volts;
  700. } else {
  701. /* If EEPROM is not populated */
  702. if (is_dra72x())
  703. *omap_vcores = &dra722_volts;
  704. else
  705. *omap_vcores = &dra752_volts;
  706. }
  707. }
  708. void set_muxconf_regs(void)
  709. {
  710. do_set_mux32((*ctrl)->control_padconf_core_base,
  711. early_padconf, ARRAY_SIZE(early_padconf));
  712. }
  713. #if defined(CONFIG_MTD_RAW_NAND)
  714. static int nand_sw_detect(void)
  715. {
  716. int rc;
  717. uchar data[2];
  718. struct udevice *dev;
  719. rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
  720. NAND_PCF8575_ADDR, 0, &dev);
  721. if (rc)
  722. return -1;
  723. rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
  724. if (rc)
  725. return -1;
  726. /* We are only interested in P10 and P11 on PCF8575 which is equal to
  727. * bits 8 and 9.
  728. */
  729. data[1] = data[1] & 0x3;
  730. /* Ensure only P11 is set and P10 is cleared. This ensures only
  731. * NAND (P10) is configured and not NOR (P11) which are both low
  732. * true signals. NAND and NOR settings should not be enabled at
  733. * the same time.
  734. */
  735. if (data[1] == 0x2)
  736. return 0;
  737. return -1;
  738. }
  739. #else
  740. int nand_sw_detect(void)
  741. {
  742. return -1;
  743. }
  744. #endif
  745. #ifdef CONFIG_IODELAY_RECALIBRATION
  746. void recalibrate_iodelay(void)
  747. {
  748. struct pad_conf_entry const *pads, *delta_pads = NULL;
  749. struct iodelay_cfg_entry const *iodelay;
  750. int npads, niodelays, delta_npads = 0;
  751. int ret;
  752. switch (omap_revision()) {
  753. case DRA722_ES1_0:
  754. case DRA722_ES2_0:
  755. case DRA722_ES2_1:
  756. pads = dra72x_core_padconf_array_common;
  757. npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
  758. if (board_is_dra71x_evm()) {
  759. pads = dra71x_core_padconf_array;
  760. npads = ARRAY_SIZE(dra71x_core_padconf_array);
  761. iodelay = dra71_iodelay_cfg_array;
  762. niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
  763. /* If SW8 on the EVM is set to enable NAND then
  764. * overwrite the pins used by VOUT3 with NAND.
  765. */
  766. if (!nand_sw_detect()) {
  767. delta_pads = dra71x_nand_padconf_array;
  768. delta_npads =
  769. ARRAY_SIZE(dra71x_nand_padconf_array);
  770. } else {
  771. delta_pads = dra71x_vout3_padconf_array;
  772. delta_npads =
  773. ARRAY_SIZE(dra71x_vout3_padconf_array);
  774. }
  775. } else if (board_is_dra72x_revc_or_later()) {
  776. delta_pads = dra72x_rgmii_padconf_array_revc;
  777. delta_npads =
  778. ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
  779. iodelay = dra72_iodelay_cfg_array_revc;
  780. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
  781. } else {
  782. delta_pads = dra72x_rgmii_padconf_array_revb;
  783. delta_npads =
  784. ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
  785. iodelay = dra72_iodelay_cfg_array_revb;
  786. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
  787. }
  788. break;
  789. case DRA752_ES1_0:
  790. case DRA752_ES1_1:
  791. pads = dra74x_core_padconf_array;
  792. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  793. iodelay = dra742_es1_1_iodelay_cfg_array;
  794. niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
  795. break;
  796. case DRA762_ACD_ES1_0:
  797. case DRA762_ES1_0:
  798. pads = dra76x_core_padconf_array;
  799. npads = ARRAY_SIZE(dra76x_core_padconf_array);
  800. iodelay = dra76x_es1_0_iodelay_cfg_array;
  801. niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
  802. break;
  803. default:
  804. case DRA752_ES2_0:
  805. case DRA762_ABZ_ES1_0:
  806. pads = dra74x_core_padconf_array;
  807. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  808. iodelay = dra742_es2_0_iodelay_cfg_array;
  809. niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
  810. /* Setup port1 and port2 for rgmii with 'no-id' mode */
  811. clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
  812. RGMII1_ID_MODE_N_MASK);
  813. break;
  814. }
  815. /* Setup I/O isolation */
  816. ret = __recalibrate_iodelay_start();
  817. if (ret)
  818. goto err;
  819. /* Do the muxing here */
  820. do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
  821. /* Now do the weird minor deltas that should be safe */
  822. if (delta_npads)
  823. do_set_mux32((*ctrl)->control_padconf_core_base,
  824. delta_pads, delta_npads);
  825. if (is_dra76x())
  826. /* Set mux for MCAN instead of DCAN1 */
  827. clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
  828. MCAN_SEL_ALT_MASK, MCAN_SEL);
  829. /* Setup IOdelay configuration */
  830. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
  831. err:
  832. /* Closeup.. remove isolation */
  833. __recalibrate_iodelay_end(ret);
  834. }
  835. #endif
  836. #if defined(CONFIG_MMC)
  837. int board_mmc_init(bd_t *bis)
  838. {
  839. omap_mmc_init(0, 0, 0, -1, -1);
  840. omap_mmc_init(1, 0, 0, -1, -1);
  841. return 0;
  842. }
  843. void board_mmc_poweron_ldo(uint voltage)
  844. {
  845. if (board_is_dra71x_evm()) {
  846. if (voltage == LDO_VOLT_3V0)
  847. voltage = 0x19;
  848. else if (voltage == LDO_VOLT_1V8)
  849. voltage = 0xa;
  850. lp873x_mmc1_poweron_ldo(voltage);
  851. } else if (board_is_dra76x_evm()) {
  852. palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
  853. } else {
  854. palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
  855. }
  856. }
  857. static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
  858. .hw_rev = "rev11",
  859. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  860. MMC_CAP(UHS_SDR104),
  861. .max_freq = 96000000,
  862. };
  863. static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
  864. .hw_rev = "rev11",
  865. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  866. MMC_CAP(UHS_SDR104) |
  867. MMC_CAP(UHS_SDR50),
  868. .max_freq = 48000000,
  869. };
  870. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  871. {
  872. switch (omap_revision()) {
  873. case DRA752_ES1_0:
  874. case DRA752_ES1_1:
  875. if (addr == OMAP_HSMMC1_BASE)
  876. return &dra7x_es1_1_mmc1_fixups;
  877. else
  878. return &dra7x_es1_1_mmc23_fixups;
  879. default:
  880. return NULL;
  881. }
  882. }
  883. #endif
  884. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  885. int spl_start_uboot(void)
  886. {
  887. /* break into full u-boot on 'c' */
  888. if (serial_tstc() && serial_getc() == 'c')
  889. return 1;
  890. #ifdef CONFIG_SPL_ENV_SUPPORT
  891. env_init();
  892. env_load();
  893. if (env_get_yesno("boot_os") != 1)
  894. return 1;
  895. #endif
  896. return 0;
  897. }
  898. #endif
  899. #ifdef CONFIG_DRIVER_TI_CPSW
  900. extern u32 *const omap_si_rev;
  901. static void cpsw_control(int enabled)
  902. {
  903. /* VTP can be added here */
  904. return;
  905. }
  906. static struct cpsw_slave_data cpsw_slaves[] = {
  907. {
  908. .slave_reg_ofs = 0x208,
  909. .sliver_reg_ofs = 0xd80,
  910. .phy_addr = 2,
  911. },
  912. {
  913. .slave_reg_ofs = 0x308,
  914. .sliver_reg_ofs = 0xdc0,
  915. .phy_addr = 3,
  916. },
  917. };
  918. static struct cpsw_platform_data cpsw_data = {
  919. .mdio_base = CPSW_MDIO_BASE,
  920. .cpsw_base = CPSW_BASE,
  921. .mdio_div = 0xff,
  922. .channels = 8,
  923. .cpdma_reg_ofs = 0x800,
  924. .slaves = 2,
  925. .slave_data = cpsw_slaves,
  926. .ale_reg_ofs = 0xd00,
  927. .ale_entries = 1024,
  928. .host_port_reg_ofs = 0x108,
  929. .hw_stats_reg_ofs = 0x900,
  930. .bd_ram_ofs = 0x2000,
  931. .mac_control = (1 << 5),
  932. .control = cpsw_control,
  933. .host_port_num = 0,
  934. .version = CPSW_CTRL_VERSION_2,
  935. };
  936. int board_eth_init(bd_t *bis)
  937. {
  938. int ret;
  939. uint8_t mac_addr[6];
  940. uint32_t mac_hi, mac_lo;
  941. uint32_t ctrl_val;
  942. /* try reading mac address from efuse */
  943. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  944. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  945. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  946. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  947. mac_addr[2] = mac_hi & 0xFF;
  948. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  949. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  950. mac_addr[5] = mac_lo & 0xFF;
  951. if (!env_get("ethaddr")) {
  952. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  953. if (is_valid_ethaddr(mac_addr))
  954. eth_env_set_enetaddr("ethaddr", mac_addr);
  955. }
  956. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  957. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  958. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  959. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  960. mac_addr[2] = mac_hi & 0xFF;
  961. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  962. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  963. mac_addr[5] = mac_lo & 0xFF;
  964. if (!env_get("eth1addr")) {
  965. if (is_valid_ethaddr(mac_addr))
  966. eth_env_set_enetaddr("eth1addr", mac_addr);
  967. }
  968. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  969. ctrl_val |= 0x22;
  970. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  971. if (*omap_si_rev == DRA722_ES1_0)
  972. cpsw_data.active_slave = 1;
  973. if (board_is_dra72x_revc_or_later()) {
  974. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
  975. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
  976. }
  977. ret = cpsw_register(&cpsw_data);
  978. if (ret < 0)
  979. printf("Error %d registering CPSW switch\n", ret);
  980. return ret;
  981. }
  982. #endif
  983. #ifdef CONFIG_BOARD_EARLY_INIT_F
  984. /* VTT regulator enable */
  985. static inline void vtt_regulator_enable(void)
  986. {
  987. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  988. return;
  989. /* Do not enable VTT for DRA722 or DRA76x */
  990. if (is_dra72x() || is_dra76x())
  991. return;
  992. /*
  993. * EVM Rev G and later use gpio7_11 for DDR3 termination.
  994. * This is safe enough to do on older revs.
  995. */
  996. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  997. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  998. }
  999. int board_early_init_f(void)
  1000. {
  1001. vtt_regulator_enable();
  1002. return 0;
  1003. }
  1004. #endif
  1005. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  1006. int ft_board_setup(void *blob, bd_t *bd)
  1007. {
  1008. ft_cpu_setup(blob, bd);
  1009. return 0;
  1010. }
  1011. #endif
  1012. #ifdef CONFIG_SPL_LOAD_FIT
  1013. int board_fit_config_name_match(const char *name)
  1014. {
  1015. if (is_dra72x()) {
  1016. if (board_is_dra71x_evm()) {
  1017. if (!strcmp(name, "dra71-evm"))
  1018. return 0;
  1019. }else if(board_is_dra72x_revc_or_later()) {
  1020. if (!strcmp(name, "dra72-evm-revc"))
  1021. return 0;
  1022. } else if (!strcmp(name, "dra72-evm")) {
  1023. return 0;
  1024. }
  1025. } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
  1026. return 0;
  1027. } else if (!is_dra72x() && !is_dra76x_acd() &&
  1028. !strcmp(name, "dra7-evm")) {
  1029. return 0;
  1030. }
  1031. return -1;
  1032. }
  1033. #endif
  1034. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  1035. int fastboot_set_reboot_flag(void)
  1036. {
  1037. printf("Setting reboot to fastboot flag ...\n");
  1038. env_set("dofastboot", "1");
  1039. env_save();
  1040. return 0;
  1041. }
  1042. #endif
  1043. #ifdef CONFIG_TI_SECURE_DEVICE
  1044. void board_fit_image_post_process(void **p_image, size_t *p_size)
  1045. {
  1046. secure_boot_verify_image(p_image, p_size);
  1047. }
  1048. void board_tee_image_process(ulong tee_image, size_t tee_size)
  1049. {
  1050. secure_tee_install((u32)tee_image);
  1051. }
  1052. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  1053. #endif