board.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM43XX based boards
  6. *
  7. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <eeprom.h>
  11. #include <env.h>
  12. #include <i2c.h>
  13. #include <init.h>
  14. #include <linux/errno.h>
  15. #include <spl.h>
  16. #include <usb.h>
  17. #include <asm/omap_sec_common.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/mux.h>
  21. #include <asm/arch/ddr_defs.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/emif.h>
  24. #include <asm/omap_common.h>
  25. #include "../common/board_detect.h"
  26. #include "board.h"
  27. #include <power/pmic.h>
  28. #include <power/tps65218.h>
  29. #include <power/tps62362.h>
  30. #include <miiphy.h>
  31. #include <cpsw.h>
  32. #include <linux/usb/gadget.h>
  33. #include <dwc3-uboot.h>
  34. #include <dwc3-omap-uboot.h>
  35. #include <ti-usb-phy-uboot.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  38. /*
  39. * Read header information from EEPROM into global structure.
  40. */
  41. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  42. void do_board_detect(void)
  43. {
  44. /* Ensure I2C is initialized for EEPROM access*/
  45. gpi2c_init();
  46. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  47. CONFIG_EEPROM_CHIP_ADDRESS))
  48. printf("ti_i2c_eeprom_init failed\n");
  49. }
  50. #endif
  51. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  52. const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  53. { /* 19.2 MHz */
  54. {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
  55. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  56. {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
  57. {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
  58. {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
  59. {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
  60. },
  61. { /* 24 MHz */
  62. {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
  63. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  64. {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
  65. {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
  66. {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
  67. {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
  68. },
  69. { /* 25 MHz */
  70. {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
  71. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  72. {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
  73. {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
  74. {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
  75. {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
  76. },
  77. { /* 26 MHz */
  78. {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
  79. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  80. {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
  81. {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
  82. {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
  83. {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
  84. },
  85. };
  86. const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  87. {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
  88. {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
  89. {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
  90. {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
  91. };
  92. const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  93. {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  94. {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
  95. {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
  96. {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
  97. };
  98. const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
  99. {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
  100. {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
  101. {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
  102. {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
  103. };
  104. const struct dpll_params gp_evm_dpll_ddr = {
  105. 50, 2, 1, -1, 2, -1, -1};
  106. static const struct dpll_params idk_dpll_ddr = {
  107. 400, 23, 1, -1, 2, -1, -1
  108. };
  109. static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
  110. 0x00500050,
  111. 0x00350035,
  112. 0x00350035,
  113. 0x00350035,
  114. 0x00350035,
  115. 0x00350035,
  116. 0x00000000,
  117. 0x00000000,
  118. 0x00000000,
  119. 0x00000000,
  120. 0x00000000,
  121. 0x00000000,
  122. 0x00000000,
  123. 0x00000000,
  124. 0x00000000,
  125. 0x00000000,
  126. 0x00000000,
  127. 0x00000000,
  128. 0x40001000,
  129. 0x08102040
  130. };
  131. const struct ctrl_ioregs ioregs_lpddr2 = {
  132. .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
  133. .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
  134. .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
  135. .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  136. .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  137. .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  138. .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  139. .emif_sdram_config_ext = 0x1,
  140. };
  141. const struct emif_regs emif_regs_lpddr2 = {
  142. .sdram_config = 0x808012BA,
  143. .ref_ctrl = 0x0000040D,
  144. .sdram_tim1 = 0xEA86B411,
  145. .sdram_tim2 = 0x103A094A,
  146. .sdram_tim3 = 0x0F6BA37F,
  147. .read_idle_ctrl = 0x00050000,
  148. .zq_config = 0x50074BE4,
  149. .temp_alert_config = 0x0,
  150. .emif_rd_wr_lvl_rmp_win = 0x0,
  151. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  152. .emif_rd_wr_lvl_ctl = 0x0,
  153. .emif_ddr_phy_ctlr_1 = 0x0E284006,
  154. .emif_rd_wr_exec_thresh = 0x80000405,
  155. .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
  156. .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
  157. .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
  158. .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
  159. .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
  160. .emif_prio_class_serv_map = 0x80000001,
  161. .emif_connect_id_serv_1_map = 0x80000094,
  162. .emif_connect_id_serv_2_map = 0x00000000,
  163. .emif_cos_config = 0x000FFFFF
  164. };
  165. const struct ctrl_ioregs ioregs_ddr3 = {
  166. .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
  167. .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
  168. .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
  169. .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
  170. .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
  171. .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  172. .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  173. .emif_sdram_config_ext = 0xc163,
  174. };
  175. const struct emif_regs ddr3_emif_regs_400Mhz = {
  176. .sdram_config = 0x638413B2,
  177. .ref_ctrl = 0x00000C30,
  178. .sdram_tim1 = 0xEAAAD4DB,
  179. .sdram_tim2 = 0x266B7FDA,
  180. .sdram_tim3 = 0x107F8678,
  181. .read_idle_ctrl = 0x00050000,
  182. .zq_config = 0x50074BE4,
  183. .temp_alert_config = 0x0,
  184. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  185. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  186. .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
  187. .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
  188. .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
  189. .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
  190. .emif_rd_wr_lvl_rmp_win = 0x0,
  191. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  192. .emif_rd_wr_lvl_ctl = 0x0,
  193. .emif_rd_wr_exec_thresh = 0x80000405,
  194. .emif_prio_class_serv_map = 0x80000001,
  195. .emif_connect_id_serv_1_map = 0x80000094,
  196. .emif_connect_id_serv_2_map = 0x00000000,
  197. .emif_cos_config = 0x000FFFFF
  198. };
  199. /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
  200. const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
  201. .sdram_config = 0x638413B2,
  202. .ref_ctrl = 0x00000C30,
  203. .sdram_tim1 = 0xEAAAD4DB,
  204. .sdram_tim2 = 0x266B7FDA,
  205. .sdram_tim3 = 0x107F8678,
  206. .read_idle_ctrl = 0x00050000,
  207. .zq_config = 0x50074BE4,
  208. .temp_alert_config = 0x0,
  209. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  210. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  211. .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
  212. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  213. .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
  214. .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
  215. .emif_rd_wr_exec_thresh = 0x80000405,
  216. .emif_prio_class_serv_map = 0x80000001,
  217. .emif_connect_id_serv_1_map = 0x80000094,
  218. .emif_connect_id_serv_2_map = 0x00000000,
  219. .emif_cos_config = 0x000FFFFF
  220. };
  221. /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
  222. const struct emif_regs ddr3_emif_regs_400Mhz_production = {
  223. .sdram_config = 0x638413B2,
  224. .ref_ctrl = 0x00000C30,
  225. .sdram_tim1 = 0xEAAAD4DB,
  226. .sdram_tim2 = 0x266B7FDA,
  227. .sdram_tim3 = 0x107F8678,
  228. .read_idle_ctrl = 0x00050000,
  229. .zq_config = 0x50074BE4,
  230. .temp_alert_config = 0x0,
  231. .emif_ddr_phy_ctlr_1 = 0x00048008,
  232. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  233. .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
  234. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  235. .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
  236. .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
  237. .emif_rd_wr_exec_thresh = 0x80000405,
  238. .emif_prio_class_serv_map = 0x80000001,
  239. .emif_connect_id_serv_1_map = 0x80000094,
  240. .emif_connect_id_serv_2_map = 0x00000000,
  241. .emif_cos_config = 0x000FFFFF
  242. };
  243. static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
  244. .sdram_config = 0x638413b2,
  245. .sdram_config2 = 0x00000000,
  246. .ref_ctrl = 0x00000c30,
  247. .sdram_tim1 = 0xeaaad4db,
  248. .sdram_tim2 = 0x266b7fda,
  249. .sdram_tim3 = 0x107f8678,
  250. .read_idle_ctrl = 0x00050000,
  251. .zq_config = 0x50074be4,
  252. .temp_alert_config = 0x0,
  253. .emif_ddr_phy_ctlr_1 = 0x0e084008,
  254. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  255. .emif_ddr_ext_phy_ctrl_2 = 0x89,
  256. .emif_ddr_ext_phy_ctrl_3 = 0x90,
  257. .emif_ddr_ext_phy_ctrl_4 = 0x8e,
  258. .emif_ddr_ext_phy_ctrl_5 = 0x8d,
  259. .emif_rd_wr_lvl_rmp_win = 0x0,
  260. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  261. .emif_rd_wr_lvl_ctl = 0x00000000,
  262. .emif_rd_wr_exec_thresh = 0x80000000,
  263. .emif_prio_class_serv_map = 0x80000001,
  264. .emif_connect_id_serv_1_map = 0x80000094,
  265. .emif_connect_id_serv_2_map = 0x00000000,
  266. .emif_cos_config = 0x000FFFFF
  267. };
  268. static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
  269. .sdram_config = 0x61a11b32,
  270. .sdram_config2 = 0x00000000,
  271. .ref_ctrl = 0x00000c30,
  272. .sdram_tim1 = 0xeaaad4db,
  273. .sdram_tim2 = 0x266b7fda,
  274. .sdram_tim3 = 0x107f8678,
  275. .read_idle_ctrl = 0x00050000,
  276. .zq_config = 0x50074be4,
  277. .temp_alert_config = 0x00000000,
  278. .emif_ddr_phy_ctlr_1 = 0x00008009,
  279. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  280. .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
  281. .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
  282. .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
  283. .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
  284. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  285. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  286. .emif_rd_wr_lvl_ctl = 0x00000000,
  287. .emif_rd_wr_exec_thresh = 0x00000405,
  288. .emif_prio_class_serv_map = 0x00000000,
  289. .emif_connect_id_serv_1_map = 0x00000000,
  290. .emif_connect_id_serv_2_map = 0x00000000,
  291. .emif_cos_config = 0x00ffffff
  292. };
  293. void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  294. {
  295. if (board_is_eposevm()) {
  296. *regs = ext_phy_ctrl_const_base_lpddr2;
  297. *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
  298. }
  299. return;
  300. }
  301. const struct dpll_params *get_dpll_ddr_params(void)
  302. {
  303. int ind = get_sys_clk_index();
  304. if (board_is_eposevm())
  305. return &epos_evm_dpll_ddr[ind];
  306. else if (board_is_evm() || board_is_sk())
  307. return &gp_evm_dpll_ddr;
  308. else if (board_is_idk())
  309. return &idk_dpll_ddr;
  310. printf(" Board '%s' not supported\n", board_ti_get_name());
  311. return NULL;
  312. }
  313. /*
  314. * get_opp_offset:
  315. * Returns the index for safest OPP of the device to boot.
  316. * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
  317. * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
  318. * This data is read from dev_attribute register which is e-fused.
  319. * A'1' in bit indicates OPP disabled and not available, a '0' indicates
  320. * OPP available. Lowest OPP starts with min_off. So returning the
  321. * bit with rightmost '0'.
  322. */
  323. static int get_opp_offset(int max_off, int min_off)
  324. {
  325. struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
  326. int opp, offset, i;
  327. /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
  328. opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
  329. for (i = max_off; i >= min_off; i--) {
  330. offset = opp & (1 << i);
  331. if (!offset)
  332. return i;
  333. }
  334. return min_off;
  335. }
  336. const struct dpll_params *get_dpll_mpu_params(void)
  337. {
  338. int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
  339. u32 ind = get_sys_clk_index();
  340. return &dpll_mpu[ind][opp];
  341. }
  342. const struct dpll_params *get_dpll_core_params(void)
  343. {
  344. int ind = get_sys_clk_index();
  345. return &dpll_core[ind];
  346. }
  347. const struct dpll_params *get_dpll_per_params(void)
  348. {
  349. int ind = get_sys_clk_index();
  350. return &dpll_per[ind];
  351. }
  352. void scale_vcores_generic(u32 m)
  353. {
  354. int mpu_vdd, ddr_volt;
  355. #ifndef CONFIG_DM_I2C
  356. if (i2c_probe(TPS65218_CHIP_PM))
  357. return;
  358. #else
  359. if (power_tps65218_init(0))
  360. return;
  361. #endif
  362. switch (m) {
  363. case 1000:
  364. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
  365. break;
  366. case 800:
  367. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
  368. break;
  369. case 720:
  370. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
  371. break;
  372. case 600:
  373. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
  374. break;
  375. case 300:
  376. mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
  377. break;
  378. default:
  379. puts("Unknown MPU clock, not scaling\n");
  380. return;
  381. }
  382. /* Set DCDC1 (CORE) voltage to 1.1V */
  383. if (tps65218_voltage_update(TPS65218_DCDC1,
  384. TPS65218_DCDC_VOLT_SEL_1100MV)) {
  385. printf("%s failure\n", __func__);
  386. return;
  387. }
  388. /* Set DCDC2 (MPU) voltage */
  389. if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
  390. printf("%s failure\n", __func__);
  391. return;
  392. }
  393. if (board_is_eposevm())
  394. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
  395. else
  396. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
  397. /* Set DCDC3 (DDR) voltage */
  398. if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
  399. printf("%s failure\n", __func__);
  400. return;
  401. }
  402. }
  403. void scale_vcores_idk(u32 m)
  404. {
  405. int mpu_vdd;
  406. #ifndef CONFIG_DM_I2C
  407. if (i2c_probe(TPS62362_I2C_ADDR))
  408. return;
  409. #else
  410. if (power_tps62362_init(0))
  411. return;
  412. #endif
  413. switch (m) {
  414. case 1000:
  415. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  416. break;
  417. case 800:
  418. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
  419. break;
  420. case 720:
  421. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
  422. break;
  423. case 600:
  424. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
  425. break;
  426. case 300:
  427. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  428. break;
  429. default:
  430. puts("Unknown MPU clock, not scaling\n");
  431. return;
  432. }
  433. /* Set VDD_MPU voltage */
  434. if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
  435. printf("%s failure\n", __func__);
  436. return;
  437. }
  438. }
  439. void gpi2c_init(void)
  440. {
  441. /* When needed to be invoked prior to BSS initialization */
  442. static bool first_time = true;
  443. if (first_time) {
  444. enable_i2c0_pin_mux();
  445. #ifndef CONFIG_DM_I2C
  446. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  447. CONFIG_SYS_OMAP24_I2C_SLAVE);
  448. #endif
  449. first_time = false;
  450. }
  451. }
  452. void scale_vcores(void)
  453. {
  454. const struct dpll_params *mpu_params;
  455. /* Ensure I2C is initialized for PMIC configuration */
  456. gpi2c_init();
  457. /* Get the frequency */
  458. mpu_params = get_dpll_mpu_params();
  459. if (board_is_idk())
  460. scale_vcores_idk(mpu_params->m);
  461. else
  462. scale_vcores_generic(mpu_params->m);
  463. }
  464. void set_uart_mux_conf(void)
  465. {
  466. enable_uart0_pin_mux();
  467. }
  468. void set_mux_conf_regs(void)
  469. {
  470. enable_board_pin_mux();
  471. }
  472. static void enable_vtt_regulator(void)
  473. {
  474. u32 temp;
  475. /* enable module */
  476. writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
  477. /* enable output for GPIO5_7 */
  478. writel(GPIO_SETDATAOUT(7),
  479. AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
  480. temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  481. temp = temp & ~(GPIO_OE_ENABLE(7));
  482. writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  483. }
  484. enum {
  485. RTC_BOARD_EPOS = 1,
  486. RTC_BOARD_EVM14,
  487. RTC_BOARD_EVM12,
  488. RTC_BOARD_GPEVM,
  489. RTC_BOARD_SK,
  490. };
  491. /*
  492. * In the rtc_only+DRR in self-refresh boot path we have the board type info
  493. * in the rtc scratch pad register hence we bypass the costly i2c reads to
  494. * eeprom and directly programthe board name string
  495. */
  496. void rtc_only_update_board_type(u32 btype)
  497. {
  498. const char *name = "";
  499. const char *rev = "1.0";
  500. switch (btype) {
  501. case RTC_BOARD_EPOS:
  502. name = "AM43EPOS";
  503. break;
  504. case RTC_BOARD_EVM14:
  505. name = "AM43__GP";
  506. rev = "1.4";
  507. break;
  508. case RTC_BOARD_EVM12:
  509. name = "AM43__GP";
  510. rev = "1.2";
  511. break;
  512. case RTC_BOARD_GPEVM:
  513. name = "AM43__GP";
  514. break;
  515. case RTC_BOARD_SK:
  516. name = "AM43__SK";
  517. break;
  518. }
  519. ti_i2c_eeprom_am_set(name, rev);
  520. }
  521. u32 rtc_only_get_board_type(void)
  522. {
  523. if (board_is_eposevm())
  524. return RTC_BOARD_EPOS;
  525. else if (board_is_evm_14_or_later())
  526. return RTC_BOARD_EVM14;
  527. else if (board_is_evm_12_or_later())
  528. return RTC_BOARD_EVM12;
  529. else if (board_is_gpevm())
  530. return RTC_BOARD_GPEVM;
  531. else if (board_is_sk())
  532. return RTC_BOARD_SK;
  533. return 0;
  534. }
  535. void sdram_init(void)
  536. {
  537. /*
  538. * EPOS EVM has 1GB LPDDR2 connected to EMIF.
  539. * GP EMV has 1GB DDR3 connected to EMIF
  540. * along with VTT regulator.
  541. */
  542. if (board_is_eposevm()) {
  543. config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
  544. } else if (board_is_evm_14_or_later()) {
  545. enable_vtt_regulator();
  546. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  547. &ddr3_emif_regs_400Mhz_production, 0);
  548. } else if (board_is_evm_12_or_later()) {
  549. enable_vtt_regulator();
  550. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  551. &ddr3_emif_regs_400Mhz_beta, 0);
  552. } else if (board_is_evm()) {
  553. enable_vtt_regulator();
  554. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  555. &ddr3_emif_regs_400Mhz, 0);
  556. } else if (board_is_sk()) {
  557. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  558. &ddr3_sk_emif_regs_400Mhz, 0);
  559. } else if (board_is_idk()) {
  560. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  561. &ddr3_idk_emif_regs_400Mhz, 0);
  562. }
  563. }
  564. #endif
  565. /* setup board specific PMIC */
  566. int power_init_board(void)
  567. {
  568. int rc;
  569. #ifndef CONFIG_DM_I2C
  570. struct pmic *p = NULL;
  571. #endif
  572. if (board_is_idk()) {
  573. rc = power_tps62362_init(0);
  574. if (rc)
  575. goto done;
  576. #ifndef CONFIG_DM_I2C
  577. p = pmic_get("TPS62362");
  578. if (!p || pmic_probe(p))
  579. goto done;
  580. #endif
  581. puts("PMIC: TPS62362\n");
  582. } else {
  583. rc = power_tps65218_init(0);
  584. if (rc)
  585. goto done;
  586. #ifndef CONFIG_DM_I2C
  587. p = pmic_get("TPS65218_PMIC");
  588. if (!p || pmic_probe(p))
  589. goto done;
  590. #endif
  591. puts("PMIC: TPS65218\n");
  592. }
  593. done:
  594. return 0;
  595. }
  596. int board_init(void)
  597. {
  598. struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
  599. u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
  600. modena_init0_bw_integer, modena_init0_watermark_0;
  601. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  602. gpmc_init();
  603. /*
  604. * Call this to initialize *ctrl again
  605. */
  606. hw_data_init();
  607. /* Clear all important bits for DSS errata that may need to be tweaked*/
  608. mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
  609. MREQPRIO_0_SAB_INIT0_MASK;
  610. mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
  611. modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
  612. BW_LIMITER_BW_FRAC_MASK;
  613. modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
  614. BW_LIMITER_BW_INT_MASK;
  615. modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
  616. BW_LIMITER_BW_WATERMARK_MASK;
  617. /* Setting MReq Priority of the DSS*/
  618. mreqprio_0 |= 0x77;
  619. /*
  620. * Set L3 Fast Configuration Register
  621. * Limiting bandwith for ARM core to 700 MBPS
  622. */
  623. modena_init0_bw_fractional |= 0x10;
  624. modena_init0_bw_integer |= 0x3;
  625. writel(mreqprio_0, &cdev->mreqprio_0);
  626. writel(mreqprio_1, &cdev->mreqprio_1);
  627. writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
  628. writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
  629. writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
  630. return 0;
  631. }
  632. #ifdef CONFIG_BOARD_LATE_INIT
  633. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  634. static int device_okay(const char *path)
  635. {
  636. int node;
  637. node = fdt_path_offset(gd->fdt_blob, path);
  638. if (node < 0)
  639. return 0;
  640. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  641. }
  642. #endif
  643. int board_late_init(void)
  644. {
  645. struct udevice *dev;
  646. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  647. set_board_info_env(NULL);
  648. /*
  649. * Default FIT boot on HS devices. Non FIT images are not allowed
  650. * on HS devices.
  651. */
  652. if (get_device_type() == HS_DEVICE)
  653. env_set("boot_fit", "1");
  654. #endif
  655. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  656. if (device_okay("/ocp/omap_dwc3@48380000"))
  657. enable_usb_clocks(0);
  658. if (device_okay("/ocp/omap_dwc3@483c0000"))
  659. enable_usb_clocks(1);
  660. #endif
  661. /* Just probe the potentially supported cdce913 device */
  662. uclass_get_device(UCLASS_CLK, 0, &dev);
  663. return 0;
  664. }
  665. #endif
  666. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  667. #ifdef CONFIG_USB_DWC3
  668. static struct dwc3_device usb_otg_ss1 = {
  669. .maximum_speed = USB_SPEED_HIGH,
  670. .base = USB_OTG_SS1_BASE,
  671. .tx_fifo_resize = false,
  672. .index = 0,
  673. };
  674. static struct dwc3_omap_device usb_otg_ss1_glue = {
  675. .base = (void *)USB_OTG_SS1_GLUE_BASE,
  676. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  677. .index = 0,
  678. };
  679. static struct ti_usb_phy_device usb_phy1_device = {
  680. .usb2_phy_power = (void *)USB2_PHY1_POWER,
  681. .index = 0,
  682. };
  683. static struct dwc3_device usb_otg_ss2 = {
  684. .maximum_speed = USB_SPEED_HIGH,
  685. .base = USB_OTG_SS2_BASE,
  686. .tx_fifo_resize = false,
  687. .index = 1,
  688. };
  689. static struct dwc3_omap_device usb_otg_ss2_glue = {
  690. .base = (void *)USB_OTG_SS2_GLUE_BASE,
  691. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  692. .index = 1,
  693. };
  694. static struct ti_usb_phy_device usb_phy2_device = {
  695. .usb2_phy_power = (void *)USB2_PHY2_POWER,
  696. .index = 1,
  697. };
  698. int usb_gadget_handle_interrupts(int index)
  699. {
  700. u32 status;
  701. status = dwc3_omap_uboot_interrupt_status(index);
  702. if (status)
  703. dwc3_uboot_handle_interrupt(index);
  704. return 0;
  705. }
  706. #endif /* CONFIG_USB_DWC3 */
  707. #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
  708. int board_usb_init(int index, enum usb_init_type init)
  709. {
  710. enable_usb_clocks(index);
  711. #ifdef CONFIG_USB_DWC3
  712. switch (index) {
  713. case 0:
  714. if (init == USB_INIT_DEVICE) {
  715. usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
  716. usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  717. dwc3_omap_uboot_init(&usb_otg_ss1_glue);
  718. ti_usb_phy_uboot_init(&usb_phy1_device);
  719. dwc3_uboot_init(&usb_otg_ss1);
  720. }
  721. break;
  722. case 1:
  723. if (init == USB_INIT_DEVICE) {
  724. usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
  725. usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  726. ti_usb_phy_uboot_init(&usb_phy2_device);
  727. dwc3_omap_uboot_init(&usb_otg_ss2_glue);
  728. dwc3_uboot_init(&usb_otg_ss2);
  729. }
  730. break;
  731. default:
  732. printf("Invalid Controller Index\n");
  733. }
  734. #endif
  735. return 0;
  736. }
  737. int board_usb_cleanup(int index, enum usb_init_type init)
  738. {
  739. #ifdef CONFIG_USB_DWC3
  740. switch (index) {
  741. case 0:
  742. case 1:
  743. if (init == USB_INIT_DEVICE) {
  744. ti_usb_phy_uboot_exit(index);
  745. dwc3_uboot_exit(index);
  746. dwc3_omap_uboot_exit(index);
  747. }
  748. break;
  749. default:
  750. printf("Invalid Controller Index\n");
  751. }
  752. #endif
  753. disable_usb_clocks(index);
  754. return 0;
  755. }
  756. #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
  757. #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  758. #ifdef CONFIG_DRIVER_TI_CPSW
  759. static void cpsw_control(int enabled)
  760. {
  761. /* Additional controls can be added here */
  762. return;
  763. }
  764. static struct cpsw_slave_data cpsw_slaves[] = {
  765. {
  766. .slave_reg_ofs = 0x208,
  767. .sliver_reg_ofs = 0xd80,
  768. .phy_addr = 16,
  769. },
  770. {
  771. .slave_reg_ofs = 0x308,
  772. .sliver_reg_ofs = 0xdc0,
  773. .phy_addr = 1,
  774. },
  775. };
  776. static struct cpsw_platform_data cpsw_data = {
  777. .mdio_base = CPSW_MDIO_BASE,
  778. .cpsw_base = CPSW_BASE,
  779. .mdio_div = 0xff,
  780. .channels = 8,
  781. .cpdma_reg_ofs = 0x800,
  782. .slaves = 1,
  783. .slave_data = cpsw_slaves,
  784. .ale_reg_ofs = 0xd00,
  785. .ale_entries = 1024,
  786. .host_port_reg_ofs = 0x108,
  787. .hw_stats_reg_ofs = 0x900,
  788. .bd_ram_ofs = 0x2000,
  789. .mac_control = (1 << 5),
  790. .control = cpsw_control,
  791. .host_port_num = 0,
  792. .version = CPSW_CTRL_VERSION_2,
  793. };
  794. int board_eth_init(bd_t *bis)
  795. {
  796. int rv;
  797. uint8_t mac_addr[6];
  798. uint32_t mac_hi, mac_lo;
  799. /* try reading mac address from efuse */
  800. mac_lo = readl(&cdev->macid0l);
  801. mac_hi = readl(&cdev->macid0h);
  802. mac_addr[0] = mac_hi & 0xFF;
  803. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  804. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  805. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  806. mac_addr[4] = mac_lo & 0xFF;
  807. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  808. if (!env_get("ethaddr")) {
  809. puts("<ethaddr> not set. Validating first E-fuse MAC\n");
  810. if (is_valid_ethaddr(mac_addr))
  811. eth_env_set_enetaddr("ethaddr", mac_addr);
  812. }
  813. mac_lo = readl(&cdev->macid1l);
  814. mac_hi = readl(&cdev->macid1h);
  815. mac_addr[0] = mac_hi & 0xFF;
  816. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  817. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  818. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  819. mac_addr[4] = mac_lo & 0xFF;
  820. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  821. if (!env_get("eth1addr")) {
  822. if (is_valid_ethaddr(mac_addr))
  823. eth_env_set_enetaddr("eth1addr", mac_addr);
  824. }
  825. if (board_is_eposevm()) {
  826. writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
  827. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
  828. cpsw_slaves[0].phy_addr = 16;
  829. } else if (board_is_sk()) {
  830. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  831. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  832. cpsw_slaves[0].phy_addr = 4;
  833. cpsw_slaves[1].phy_addr = 5;
  834. } else if (board_is_idk()) {
  835. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  836. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  837. cpsw_slaves[0].phy_addr = 0;
  838. } else {
  839. writel(RGMII_MODE_ENABLE, &cdev->miisel);
  840. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  841. cpsw_slaves[0].phy_addr = 0;
  842. }
  843. rv = cpsw_register(&cpsw_data);
  844. if (rv < 0)
  845. printf("Error %d registering CPSW switch\n", rv);
  846. return rv;
  847. }
  848. #endif
  849. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  850. int ft_board_setup(void *blob, bd_t *bd)
  851. {
  852. ft_cpu_setup(blob, bd);
  853. return 0;
  854. }
  855. #endif
  856. #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
  857. int board_fit_config_name_match(const char *name)
  858. {
  859. bool eeprom_read = board_ti_was_eeprom_read();
  860. if (!strcmp(name, "am4372-generic") && !eeprom_read)
  861. return 0;
  862. else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
  863. return 0;
  864. else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
  865. return 0;
  866. else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
  867. return 0;
  868. else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
  869. return 0;
  870. else
  871. return -1;
  872. }
  873. #endif
  874. #ifdef CONFIG_DTB_RESELECT
  875. int embedded_dtb_select(void)
  876. {
  877. do_board_detect();
  878. fdtdec_setup();
  879. return 0;
  880. }
  881. #endif
  882. #ifdef CONFIG_TI_SECURE_DEVICE
  883. void board_fit_image_post_process(void **p_image, size_t *p_size)
  884. {
  885. secure_boot_verify_image(p_image, p_size);
  886. }
  887. void board_tee_image_process(ulong tee_image, size_t tee_size)
  888. {
  889. secure_tee_install((u32)tee_image);
  890. }
  891. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  892. #endif