theadorable.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <console.h>
  7. #include <i2c.h>
  8. #include <init.h>
  9. #include <pci.h>
  10. #if !defined(CONFIG_SPL_BUILD)
  11. #include <bootcount.h>
  12. #endif
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/soc.h>
  17. #include <linux/mbus.h>
  18. #ifdef CONFIG_NET
  19. #include <netdev.h>
  20. #endif
  21. #include <u-boot/crc.h>
  22. #include "theadorable.h"
  23. #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  24. #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
  27. #define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
  28. (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
  29. #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
  30. #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
  31. #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
  32. #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
  33. #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
  34. #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
  35. #define GPIO_USB0_PWR_ON 18
  36. #define GPIO_USB1_PWR_ON 19
  37. #define PEX_SWITCH_NOT_FOUNT_LIMIT 3
  38. #define STM_I2C_BUS 1
  39. #define STM_I2C_ADDR 0x27
  40. #define REBOOT_DELAY 1000 /* reboot-delay in ms */
  41. #define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */
  42. /* DDR3 static configuration */
  43. static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
  44. {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
  45. {0x00001404, 0x30000800}, /* Dunit Control Low Register */
  46. {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
  47. {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
  48. {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
  49. {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
  50. {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
  51. {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
  52. {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
  53. {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
  54. {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
  55. {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
  56. {0x000014A8, 0x00000101}, /* AXI Control Register */
  57. /*
  58. * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
  59. * training sequence
  60. */
  61. {0x000200e8, 0x3fff0e01},
  62. {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
  63. {0x0001504, 0x7fffffe1}, /* CS0 Size */
  64. {0x000150C, 0x00000000}, /* CS1 Size */
  65. {0x0001514, 0x00000000}, /* CS2 Size */
  66. {0x000151C, 0x00000000}, /* CS3 Size */
  67. {0x00020220, 0x00000007}, /* Reserved */
  68. {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
  69. {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
  70. {0x000015D0, 0x00000650}, /* MR0 */
  71. {0x000015D4, 0x00000044}, /* MR1 */
  72. {0x000015D8, 0x00000010}, /* MR2 */
  73. {0x000015DC, 0x00000000}, /* MR3 */
  74. {0x000015E0, 0x00000001},
  75. {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
  76. {0x000015EC, 0xf800a225}, /* DDR PHY */
  77. /* Recommended Settings from Marvell for 4 x 16 bit devices: */
  78. {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
  79. {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
  80. {0x0, 0x0}
  81. };
  82. static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
  83. {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
  84. };
  85. extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
  86. /*
  87. * Lane0 - PCIE0.0 X1 (to WIFI Module)
  88. * Lane5 - SATA0
  89. * Lane6 - SATA1
  90. * Lane7 - SGMII0 (to Ethernet Phy)
  91. * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
  92. * all other lanes are disabled
  93. */
  94. MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
  95. { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
  96. { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
  97. PEX_BUS_DISABLED },
  98. 0x0060, serdes_change_m_phy
  99. },
  100. };
  101. /*
  102. * Define a board-specific detection pulse-width array for the SerDes PCIe
  103. * interfaces. If not defined in the board code, the default of currently 2
  104. * is used. Values from 0...3 are possible (2 bits).
  105. */
  106. u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
  107. MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
  108. {
  109. /* Only one mode supported for this board */
  110. return &board_ddr_modes[0];
  111. }
  112. MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
  113. {
  114. return &theadorable_serdes_cfg[0];
  115. }
  116. u8 board_sat_r_get(u8 dev_num, u8 reg)
  117. {
  118. /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
  119. return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
  120. }
  121. int board_early_init_f(void)
  122. {
  123. /* Configure MPP */
  124. writel(0x00000000, MVEBU_MPP_BASE + 0x00);
  125. writel(0x03300000, MVEBU_MPP_BASE + 0x04);
  126. writel(0x00000033, MVEBU_MPP_BASE + 0x08);
  127. writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
  128. writel(0x11110000, MVEBU_MPP_BASE + 0x10);
  129. writel(0x00221100, MVEBU_MPP_BASE + 0x14);
  130. writel(0x00000000, MVEBU_MPP_BASE + 0x18);
  131. writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
  132. writel(0x00000000, MVEBU_MPP_BASE + 0x20);
  133. /* Configure GPIO */
  134. writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  135. writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  136. writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  137. writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  138. writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
  139. writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
  140. return 0;
  141. }
  142. int board_init(void)
  143. {
  144. int ret;
  145. /* adress of boot parameters */
  146. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  147. /*
  148. * Map SPI devices via MBUS so that they can be accessed via
  149. * the SPI direct access mode
  150. */
  151. mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
  152. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
  153. mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
  154. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
  155. /*
  156. * Set RX Channel Control 0 Register:
  157. * Tests have shown, that setting the LPF_COEF from 0 (1/8)
  158. * to 3 (1/1) results in a more stable USB connection.
  159. */
  160. setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
  161. setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
  162. setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
  163. /* Toggle USB power */
  164. ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
  165. if (ret < 0)
  166. return ret;
  167. gpio_direction_output(GPIO_USB0_PWR_ON, 0);
  168. ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
  169. if (ret < 0)
  170. return ret;
  171. gpio_direction_output(GPIO_USB1_PWR_ON, 0);
  172. mdelay(1);
  173. gpio_set_value(GPIO_USB0_PWR_ON, 1);
  174. gpio_set_value(GPIO_USB1_PWR_ON, 1);
  175. return 0;
  176. }
  177. int checkboard(void)
  178. {
  179. board_fpga_add();
  180. return 0;
  181. }
  182. #ifdef CONFIG_NET
  183. int board_eth_init(bd_t *bis)
  184. {
  185. cpu_eth_init(bis); /* Built in controller(s) come first */
  186. return pci_eth_init(bis);
  187. }
  188. #endif
  189. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
  190. int board_late_init(void)
  191. {
  192. pci_dev_t bdf;
  193. ulong bootcount;
  194. /*
  195. * Check if the PEX switch is detected (somtimes its not available
  196. * on the PCIe bus). In this case, try to recover by issuing a
  197. * soft-reset or even a power-cycle, depending on the bootcounter
  198. * value.
  199. */
  200. bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
  201. if (bdf == -1) {
  202. unsigned long start_time = get_timer(0);
  203. u8 i2c_buf[8];
  204. int ret;
  205. /* PEX switch not found! */
  206. bootcount = bootcount_load();
  207. printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
  208. bootcount);
  209. /*
  210. * The user can exit this boot-loop in the error case by
  211. * hitting Ctrl-C. So wait some time for this key here.
  212. */
  213. printf("Continue booting with Ctrl-C, otherwise rebooting\n");
  214. do {
  215. /* Handle control-c and timeouts */
  216. if (ctrlc()) {
  217. printf("PEX error boot-loop aborted!\n");
  218. return 0;
  219. }
  220. } while (get_timer(start_time) < ABORT_TIMEOUT);
  221. /*
  222. * At this stage the bootcounter has not been incremented
  223. * yet. We need to do this manually here to get an actually
  224. * working bootcounter in this error case.
  225. */
  226. bootcount_inc();
  227. if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
  228. printf("Issuing power-switch via uC!\n");
  229. printf("Issuing power-switch via uC!\n");
  230. i2c_set_bus_num(STM_I2C_BUS);
  231. i2c_buf[0] = STM_I2C_ADDR << 1;
  232. i2c_buf[1] = 0xc5; /* cmd */
  233. i2c_buf[2] = 0x01; /* enable */
  234. /* Delay before reboot */
  235. i2c_buf[3] = REBOOT_DELAY & 0x00ff;
  236. i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
  237. /* Delay before shutdown */
  238. i2c_buf[5] = 0x00;
  239. i2c_buf[6] = 0x00;
  240. i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
  241. ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
  242. if (ret) {
  243. printf("I2C write error (ret=%d)\n", ret);
  244. printf("Issuing soft-reset...\n");
  245. /* default handling: SOFT reset */
  246. do_reset(NULL, 0, 0, NULL);
  247. }
  248. /* Wait for power-cycle to occur... */
  249. printf("Waiting for power-cycle via uC...\n");
  250. while (1)
  251. ;
  252. } else {
  253. printf("Issuing soft-reset...\n");
  254. /* default handling: SOFT reset */
  255. do_reset(NULL, 0, 0, NULL);
  256. }
  257. }
  258. return 0;
  259. }
  260. #endif
  261. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
  262. int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  263. {
  264. pci_dev_t bdf;
  265. u16 ven_id, dev_id;
  266. if (argc != 3)
  267. return cmd_usage(cmdtp);
  268. ven_id = simple_strtoul(argv[1], NULL, 16);
  269. dev_id = simple_strtoul(argv[2], NULL, 16);
  270. printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
  271. ven_id, dev_id);
  272. /*
  273. * Check if the PCIe device is detected (somtimes its not available
  274. * on the PCIe bus)
  275. */
  276. bdf = pci_find_device(ven_id, dev_id, 0);
  277. if (bdf == -1) {
  278. /* PCIe device not found! */
  279. printf("Failed to find PCIe device\n");
  280. } else {
  281. /* PCIe device found! */
  282. printf("PCIe device found, resetting board...\n");
  283. /* default handling: SOFT reset */
  284. do_reset(NULL, 0, 0, NULL);
  285. }
  286. return 0;
  287. }
  288. U_BOOT_CMD(
  289. pcie, 3, 0, do_pcie_test,
  290. "Test for presence of a PCIe device",
  291. "<VendorID> <DeviceID>"
  292. );
  293. #endif