sys_clk.c 7.5 KB

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  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. void show_sys_clk(void)
  8. {
  9. unsigned int read = 0;
  10. read = *(volatile unsigned int*)(0x3fff77120);
  11. debug("CPU_CLK = %dMHz\n", read / 1000);
  12. read = *(volatile unsigned int*)(0x3fff77124);
  13. debug("AXI_CLK = %dMHz\n", read / 1000);
  14. read = *(volatile unsigned int*)(0x3fff77130);
  15. debug("AHB_CLK = %dMHz\n", read / 1000);
  16. read = *(volatile unsigned int*)(0x3fff77140);
  17. debug("NPU_CLK = %dMHz\n", read / 1000);
  18. read = *(volatile unsigned int*)(0x3fff7712c);
  19. debug("DDR_CK = %d MT\n", read / 1000 * 4);
  20. }
  21. void cpu_clk_config(int cpu_freq)
  22. {
  23. unsigned int read, i;
  24. for (i = 0; i < 0x40; i++) {
  25. *(volatile unsigned int*)(0x3fff78040) = 0x0; //reset ddr
  26. }
  27. //Wait ALL PLLs lock
  28. read = *(volatile unsigned int*)(0x3fff77060);
  29. while ((read & 0x1f) != 0x1f) {
  30. read = *(volatile unsigned int*)(0x3fff77060);
  31. }
  32. //enable dpu_clk
  33. *(volatile unsigned int*)(0x3fff77098) = 0x01601212;//div en
  34. *(volatile unsigned int*)(0x3fff77098) = 0x11611212;//pixclk_en, hclk_en
  35. //enable gpu_clk, 500MHz/500MHz
  36. *(volatile unsigned int*)(0x3fff7709c) = 0x11212; //gpu_hclk_en, gpu_aclk_div, gpu_cclk_div
  37. *(volatile unsigned int*)(0x3fff77070) = 0x871; //AXI BUS 2:1
  38. read = *(volatile unsigned int*)(0x3fff77070); //wait
  39. *(volatile unsigned int*)(0x3fff77070) = 0x879; //sync
  40. asm("nop"); //MUST NOT REVISE
  41. asm("nop");
  42. asm("nop");
  43. asm("nop");
  44. asm("nop");
  45. asm("nop");
  46. asm("nop");
  47. asm("nop");
  48. asm("nop");
  49. asm("nop");
  50. *(volatile unsigned int*)(0x3fff77090) = 0x1302;
  51. read = *(volatile unsigned int*)(0x3fff77090); //wait
  52. *(volatile unsigned int*)(0x3fff77090) = 0x9b0a; //sync
  53. asm("nop"); //MUST NOT REVISE
  54. asm("nop");
  55. asm("nop");
  56. asm("nop");
  57. asm("nop");
  58. asm("nop");
  59. asm("nop");
  60. asm("nop");
  61. asm("nop");
  62. asm("nop");
  63. *(volatile unsigned int*)(0x3fff77070) = 0x809;
  64. asm("nop"); //MUST NOT REVISE
  65. asm("nop");
  66. asm("nop");
  67. asm("nop");
  68. asm("nop");
  69. asm("nop");
  70. asm("nop");
  71. asm("nop");
  72. asm("nop");
  73. asm("nop");
  74. asm("nop");
  75. asm("nop");
  76. asm("nop");
  77. asm("nop");
  78. asm("nop");
  79. asm("nop");
  80. asm("nop");
  81. asm("nop");
  82. asm("nop");
  83. asm("nop");
  84. //PLLF, C910/C860 clock
  85. switch (cpu_freq) {
  86. case 2000:
  87. *(volatile unsigned int*)(0x3fff7704c) = 0x0110fa03; //2000MHz, 2000MHz
  88. break;
  89. case 1900:
  90. *(volatile unsigned int*)(0x3fff7704c) = 0x01104f01; //1896MHz, 1896MHz
  91. break;
  92. case 1800:
  93. *(volatile unsigned int*)(0x3fff7704c) = 0x01104b01; //1800MHz, 1800MHz
  94. break;
  95. case 1700:
  96. *(volatile unsigned int*)(0x3fff7704c) = 0x01104701; //1704MHz, 1704MHz
  97. break;
  98. case 1600:
  99. *(volatile unsigned int*)(0x3fff7704c) = 0x0110c803; //1600MHz, 1600MHz
  100. break;
  101. case 1500:
  102. *(volatile unsigned int*)(0x3fff7704c) = 0x01107d02; //1500MHz, 1500MHz
  103. break;
  104. case 1400:
  105. *(volatile unsigned int*)(0x3fff7704c) = 0x01103a01; //1392MHz, 1392MHz
  106. break;
  107. case 1300:
  108. *(volatile unsigned int*)(0x3fff7704c) = 0x01103601; //1296MHz, 1296MHz
  109. break;
  110. case 1200: //max legal freq for the ICE
  111. *(volatile unsigned int*)(0x3fff7704c) = 0x01103201; //1200MHz, 1200MHz
  112. break;
  113. case 1100:
  114. *(volatile unsigned int*)(0x3fff7704c) = 0x01205b01; //2184MHz, 1092MHz
  115. break;
  116. case 1000:
  117. *(volatile unsigned int*)(0x3fff7704c) = 0x0120fa03; //2000MHz, 1000MHz
  118. break;
  119. case 900:
  120. *(volatile unsigned int*)(0x3fff7704c) = 0x01204b01; //1800MHz, 900MHz
  121. break;
  122. case 800:
  123. *(volatile unsigned int*)(0x3fff7704c) = 0x0120c803; //1600MHz, 800MHz
  124. break;
  125. case 700:
  126. *(volatile unsigned int*)(0x3fff7704c) = 0x01203a01; //1392MHz, 696MHz
  127. break;
  128. case 600:
  129. *(volatile unsigned int*)(0x3fff7704c) = 0x01203201; //1200MHz, 600MHz
  130. break;
  131. case 500:
  132. *(volatile unsigned int*)(0x3fff7704c) = 0x0140fa03; //2000MHz, 500MHz
  133. break;
  134. }
  135. *(volatile unsigned int*)(0x3fff77050) = 0x03000000;
  136. *(volatile unsigned int*)(0x3fff77054) = 0x3; //reconfig
  137. read = *(volatile unsigned int*)(0x3fff7704c); //readback
  138. //Wait ALL PLLs Lock
  139. read = *(volatile unsigned int*)(0x3fff77060);
  140. read = *(volatile unsigned int*)(0x3fff77060);
  141. read = *(volatile unsigned int*)(0x3fff77060);
  142. while ((read & 0x3f) != 0x3f) {
  143. read = *(volatile unsigned int*)(0x3fff77060);
  144. }
  145. *(volatile unsigned int*)(0x3fe830470) = 0x11; //AXI BUS 2:1
  146. read = *(volatile unsigned int*)(0x3fe830470); //wait
  147. *(volatile unsigned int*)(0x3fe830470) = 0x19; //sync
  148. asm("nop"); //MUST NOT REVISE
  149. asm("nop");
  150. asm("nop");
  151. asm("nop");
  152. asm("nop");
  153. asm("nop");
  154. asm("nop");
  155. asm("nop");
  156. asm("nop");
  157. asm("nop");
  158. *(volatile unsigned int*)(0x3fe830470) = 0x9; //switch
  159. asm("nop"); //MUST NOT REVISE
  160. asm("nop");
  161. asm("nop");
  162. asm("nop");
  163. asm("nop");
  164. asm("nop");
  165. asm("nop");
  166. asm("nop");
  167. asm("nop");
  168. *(volatile unsigned int*)(0x3fff77094) = 0xffffffff;
  169. *(volatile unsigned int*)(0x3fff770a0) = 0xfff;
  170. *(volatile unsigned int*)(0x3fff78044) = 0xff;
  171. //SDIO0/1
  172. *(volatile unsigned int*)(0x3fff77078) = 0x0c800c80;
  173. }
  174. void ddr_clk_config(int ddr_freq)
  175. {
  176. unsigned int read;
  177. //DDRC clock
  178. switch (ddr_freq) {
  179. case 3192:
  180. *(volatile unsigned int*)(0x3fff77020) = 0x01208502; //798MHz, 3192MT
  181. break;
  182. case 3008:
  183. *(volatile unsigned int*)(0x3fff77020) = 0x01305e01; //752MHz, 3008MT
  184. break;
  185. case 2912:
  186. *(volatile unsigned int*)(0x3fff77020) = 0x01305b01; //728MHz, 2912MT
  187. break;
  188. case 2816:
  189. *(volatile unsigned int*)(0x3fff77020) = 0x01305801; //704MHz, 2816MT
  190. break;
  191. case 2720:
  192. *(volatile unsigned int*)(0x3fff77020) = 0x01305501; //680MHz, 2720MT
  193. break;
  194. case 2656:
  195. *(volatile unsigned int*)(0x3fff77020) = 0x01305301; //664MHz, 2656MT
  196. break;
  197. case 2592:
  198. *(volatile unsigned int*)(0x3fff77020) = 0x01305101; //648MHz, 2592MT
  199. break;
  200. case 2496:
  201. *(volatile unsigned int*)(0x3fff77020) = 0x01304e01; //624MHz, 2496MT
  202. break;
  203. case 2400:
  204. *(volatile unsigned int*)(0x3fff77020) = 0x01406401; //600MHz, 2400MT
  205. break;
  206. case 2184:
  207. *(volatile unsigned int*)(0x3fff77020) = 0x01405b01; //546MHz, 2184MT
  208. break;
  209. case 2133:
  210. *(volatile unsigned int*)(0x3fff77020) = 0x01405801; //528MHz, 2112MT
  211. break;
  212. case 2000:
  213. *(volatile unsigned int*)(0x3fff77020) = 0x01607d01; //500MHz, 2000MT
  214. break;
  215. case 1800:
  216. *(volatile unsigned int*)(0x3fff77020) = 0x01404b01; //450MHz, 1800MT
  217. break;
  218. case 1600:
  219. *(volatile unsigned int*)(0x3fff77020) = 0x01606401; //400MHz, 1600MT
  220. break;
  221. case 1392:
  222. *(volatile unsigned int*)(0x3fff77020) = 0x01605701; //348MHz, 1392MT
  223. break;
  224. default:
  225. *(volatile unsigned int*)(0x3fff77020) = 0x01604b01; //300MHz, 1200MT
  226. break;
  227. }
  228. *(volatile unsigned int*)(0x3fff77024) = 0x03000000;
  229. *(volatile unsigned int*)(0x3fff77028) = 0x3; //reconfig
  230. read = *(volatile unsigned int*)(0x3fff77020); //readback
  231. //Wait ALL PLLs Lock
  232. read = *(volatile unsigned int*)(0x3fff77060);
  233. read = *(volatile unsigned int*)(0x3fff77060);
  234. read = *(volatile unsigned int*)(0x3fff77060);
  235. while ((read & 0x1f) != 0x1f) {
  236. read = *(volatile unsigned int*)(0x3fff77060);
  237. }
  238. //enable ddr_axi clocks
  239. *(volatile unsigned int*)(0x3fff78040) = 0x0;
  240. *(volatile unsigned int*)(0x3fff78040) = 0x0;
  241. *(volatile unsigned int*)(0x3fff78040) = 0x0;
  242. *(volatile unsigned int*)(0x3fff78040) = 0x0;
  243. *(volatile unsigned int*)(0x3fff77108) = 0x1ff;
  244. *(volatile unsigned int*)(0x3fff77108) = 0x1ff;
  245. *(volatile unsigned int*)(0x3fff77108) = 0x1ff;
  246. *(volatile unsigned int*)(0x3fff78040) = 0x0;
  247. *(volatile unsigned int*)(0x3fff78040) = 0x0;
  248. *(volatile unsigned int*)(0x3fff78040) = 0x0;
  249. *(volatile unsigned int*)(0x3fff78040) = 0x0;
  250. *(volatile unsigned int*)(0x3fff78040) = 0x9;
  251. *(volatile unsigned int*)(0x3fff78040) = 0x9;
  252. //disable wdg
  253. *(volatile unsigned int*)(0x3fff78000) = 0x5ada7200;
  254. *(volatile unsigned int*)(0x3fff78010) = 0x0;
  255. }