spl.c 1.8 KB

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  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <linux/types.h>
  7. #include <common.h>
  8. #include <console.h>
  9. #include <asm/csr.h>
  10. #include <asm/io.h>
  11. #include <spl.h>
  12. #include <asm/spl.h>
  13. extern char init_ddr[];
  14. extern void cpu_clk_config(int cpu_freq);
  15. extern void ddr_clk_config(int ddr_freq);
  16. extern void show_sys_clk(void);
  17. void setup_dev_pmp(void)
  18. {
  19. /* peripherals: 0x3 f000 0000 ~ 0x4 0000 0000 napot rw */
  20. csr_write(pmpaddr2, 0x3f0000000 >> 2 | ((0x10000000 - 1) >> 3));
  21. csr_write(pmpcfg0, 0x88980000001b1f1d);
  22. }
  23. void setup_ddr_pmp(void)
  24. {
  25. /* ddr: 0x0 00000000 ~ 0x1 00000000 */
  26. csr_write(pmpaddr0, 0x0 >> 2 | ((0x100000000 - 1) >> 3));
  27. /* Leave pmpaddr1 for SDRAM on which this code is running */
  28. /* Plus, this was set in bootrom */
  29. csr_write(pmpaddr3, 0x0);
  30. csr_write(pmpaddr4, 0x0);
  31. csr_write(pmpaddr5, 0x0);
  32. csr_write(pmpcfg0, 0x88980000001b1f1f);
  33. }
  34. void cpu_performance_enable(void)
  35. {
  36. csr_write(CSR_MCOR, 0x70013);
  37. csr_write(CSR_MCCR2, 0xe0410009);
  38. csr_write(CSR_MHCR, 0x11ff);
  39. csr_write(CSR_MXSTATUS, 0x638000);
  40. csr_write(CSR_MHINT, 0x16e30c);
  41. }
  42. void board_init_f(ulong dummy)
  43. {
  44. int ddr_freq = 1600;
  45. int cpu_freq = 1200;
  46. int ret;
  47. void (*ddr_initialize)(void);
  48. setup_dev_pmp();
  49. cpu_clk_config(cpu_freq);
  50. ret = spl_early_init();
  51. if (ret) {
  52. printf("spl_early_init() failed: %d\n", ret);
  53. hang();
  54. }
  55. arch_cpu_init_dm();
  56. preloader_console_init();
  57. ddr_clk_config(ddr_freq);
  58. ddr_initialize = (void (*)(void))(init_ddr);
  59. ddr_initialize();
  60. show_sys_clk();
  61. setup_ddr_pmp();
  62. }
  63. void board_boot_order(u32 *spl_boot_list)
  64. {
  65. if ((readl((void *)0x3fff72050) & 0x3) == 3) {
  66. debug("Wait here for JTAG/GDB connecting\n");
  67. asm volatile ("ebreak");
  68. } else {
  69. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  70. cpu_performance_enable();
  71. }
  72. }