spl.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Technexion Ltd.
  4. *
  5. * Author: Richard Hu <richard.hu@technexion.com>
  6. * Fabio Estevam <festevam@gmail.com>
  7. */
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <linux/errno.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/video.h>
  16. #include <mmc.h>
  17. #include <fsl_esdhc_imx.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <spl.h>
  22. #if defined(CONFIG_SPL_BUILD)
  23. #include <asm/arch/mx6-ddr.h>
  24. #define IMX6DQ_DRIVE_STRENGTH 0x30
  25. #define IMX6SDL_DRIVE_STRENGTH 0x28
  26. #ifdef CONFIG_SPL_OS_BOOT
  27. int spl_start_uboot(void)
  28. {
  29. /* Break into full U-Boot on 'c' */
  30. if (serial_tstc() && serial_getc() == 'c')
  31. return 1;
  32. return 0;
  33. }
  34. #endif
  35. /* configure MX6Q/DUAL mmdc DDR io registers */
  36. static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  37. .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  38. .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  39. .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  40. .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  41. .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  42. .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  43. .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  44. .dram_sdba2 = 0x00000000,
  45. .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  46. .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  47. .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  48. .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  49. .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  50. .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  51. .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  52. .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  53. .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  54. .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  55. .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  56. .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  57. .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  58. .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  59. .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  60. .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  61. .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  62. .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  63. };
  64. /* configure MX6Q/DUAL mmdc GRP io registers */
  65. static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  66. .grp_ddr_type = 0x000c0000,
  67. .grp_ddrmode_ctl = 0x00020000,
  68. .grp_ddrpke = 0x00000000,
  69. .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  70. .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  71. .grp_ddrmode = 0x00020000,
  72. .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  73. .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  74. .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  75. .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  76. .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  77. .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  78. .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  79. .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  80. };
  81. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  82. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  83. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  84. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  85. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  86. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  87. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  88. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  89. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  90. .dram_sdba2 = 0x00000000,
  91. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  92. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  93. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  94. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  95. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  96. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  97. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  98. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  99. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  100. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  101. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  102. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  103. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  104. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  105. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  106. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  107. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  108. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  109. };
  110. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  111. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  112. .grp_ddr_type = 0x000c0000,
  113. .grp_ddrmode_ctl = 0x00020000,
  114. .grp_ddrpke = 0x00000000,
  115. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  116. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  117. .grp_ddrmode = 0x00020000,
  118. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  119. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  120. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  121. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  122. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  123. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  124. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  125. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  126. };
  127. /* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
  128. static struct mx6_ddr3_cfg h5t04g63afr = {
  129. .mem_speed = 800,
  130. .density = 4,
  131. .width = 16,
  132. .banks = 8,
  133. .rowaddr = 15,
  134. .coladdr = 10,
  135. .pagesz = 2,
  136. .trcd = 1500,
  137. .trcmin = 5250,
  138. .trasmin = 3750,
  139. };
  140. /* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
  141. static struct mx6_ddr3_cfg h5tq2g63ffr = {
  142. .mem_speed = 800,
  143. .density = 2,
  144. .width = 16,
  145. .banks = 8,
  146. .rowaddr = 14,
  147. .coladdr = 10,
  148. .pagesz = 2,
  149. .trcd = 1500,
  150. .trcmin = 5250,
  151. .trasmin = 3750,
  152. };
  153. static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
  154. .p0_mpwldectrl0 = 0x00000000,
  155. .p0_mpwldectrl1 = 0x00000000,
  156. .p1_mpwldectrl0 = 0x00000000,
  157. .p1_mpwldectrl1 = 0x00000000,
  158. .p0_mpdgctrl0 = 0x032C0340,
  159. .p0_mpdgctrl1 = 0x03300324,
  160. .p1_mpdgctrl0 = 0x032C0338,
  161. .p1_mpdgctrl1 = 0x03300274,
  162. .p0_mprddlctl = 0x423A383E,
  163. .p1_mprddlctl = 0x3638323E,
  164. .p0_mpwrdlctl = 0x363C4640,
  165. .p1_mpwrdlctl = 0x4034423C,
  166. };
  167. /* DDR 32bit */
  168. static struct mx6_ddr_sysinfo mem_s = {
  169. .dsize = 1,
  170. .cs1_mirror = 0,
  171. /* config for full 4GB range so that get_mem_size() works */
  172. .cs_density = 32,
  173. .ncs = 1,
  174. .bi_on = 1,
  175. .rtt_nom = 1,
  176. .rtt_wr = 0,
  177. .ralat = 5,
  178. .walat = 0,
  179. .mif3_mode = 3,
  180. .rst_to_cke = 0x23,
  181. .sde_to_rst = 0x10,
  182. };
  183. static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
  184. .p0_mpwldectrl0 = 0x001f001f,
  185. .p0_mpwldectrl1 = 0x001f001f,
  186. .p1_mpwldectrl0 = 0x001f001f,
  187. .p1_mpwldectrl1 = 0x001f001f,
  188. .p0_mpdgctrl0 = 0x420e020e,
  189. .p0_mpdgctrl1 = 0x02000200,
  190. .p1_mpdgctrl0 = 0x42020202,
  191. .p1_mpdgctrl1 = 0x01720172,
  192. .p0_mprddlctl = 0x494c4f4c,
  193. .p1_mprddlctl = 0x4a4c4c49,
  194. .p0_mpwrdlctl = 0x3f3f3133,
  195. .p1_mpwrdlctl = 0x39373f2e,
  196. };
  197. static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
  198. .p0_mpwldectrl0 = 0x0040003c,
  199. .p0_mpwldectrl1 = 0x0032003e,
  200. .p0_mpdgctrl0 = 0x42350231,
  201. .p0_mpdgctrl1 = 0x021a0218,
  202. .p0_mprddlctl = 0x4b4b4e49,
  203. .p0_mpwrdlctl = 0x3f3f3035,
  204. };
  205. static void ccgr_init(void)
  206. {
  207. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  208. writel(0x00C03F3F, &ccm->CCGR0);
  209. writel(0x0030FC03, &ccm->CCGR1);
  210. writel(0x0FFFC000, &ccm->CCGR2);
  211. writel(0x3FF03000, &ccm->CCGR3);
  212. writel(0x00FFF300, &ccm->CCGR4);
  213. writel(0x0F0000C3, &ccm->CCGR5);
  214. writel(0x000003FF, &ccm->CCGR6);
  215. }
  216. static void spl_dram_init(void)
  217. {
  218. if (is_mx6solo()) {
  219. mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  220. mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
  221. } else if (is_mx6dl()) {
  222. mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  223. mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
  224. } else if (is_mx6dq()) {
  225. mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
  226. mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
  227. }
  228. udelay(100);
  229. }
  230. void board_init_f(ulong dummy)
  231. {
  232. ccgr_init();
  233. /* setup AIPS and disable watchdog */
  234. arch_cpu_init();
  235. gpr_init();
  236. /* iomux */
  237. board_early_init_f();
  238. /* setup GP timer */
  239. timer_init();
  240. /* UART clocks enabled and gd valid - init serial console */
  241. preloader_console_init();
  242. /* DDR initialization */
  243. spl_dram_init();
  244. }
  245. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  246. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  247. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  248. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  249. {USDHC3_BASE_ADDR},
  250. };
  251. static iomux_v3_cfg_t const usdhc3_pads[] = {
  252. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  253. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  254. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  255. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  256. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  257. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  258. /* SOM MicroSD Card Detect */
  259. IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  260. };
  261. int board_mmc_getcd(struct mmc *mmc)
  262. {
  263. return 1;
  264. }
  265. int board_mmc_init(bd_t *bis)
  266. {
  267. SETUP_IOMUX_PADS(usdhc3_pads);
  268. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  269. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  270. }
  271. #endif
  272. #ifdef CONFIG_SPL_LOAD_FIT
  273. int board_fit_config_name_match(const char *name)
  274. {
  275. if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
  276. return 0;
  277. else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
  278. return 0;
  279. return -EINVAL;
  280. }
  281. #endif