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- // SPDX-License-Identifier: GPL-2.0+
- /*
- * Copyright (C) 2015 Technexion Ltd.
- *
- * Author: Richard Hu <richard.hu@technexion.com>
- * Fabio Estevam <festevam@gmail.com>
- */
- #include <asm/arch/clock.h>
- #include <asm/arch/imx-regs.h>
- #include <asm/arch/iomux.h>
- #include <asm/arch/mx6-pins.h>
- #include <linux/errno.h>
- #include <asm/gpio.h>
- #include <asm/mach-imx/iomux-v3.h>
- #include <asm/mach-imx/video.h>
- #include <mmc.h>
- #include <fsl_esdhc_imx.h>
- #include <asm/arch/crm_regs.h>
- #include <asm/io.h>
- #include <asm/arch/sys_proto.h>
- #include <spl.h>
- #if defined(CONFIG_SPL_BUILD)
- #include <asm/arch/mx6-ddr.h>
- #define IMX6DQ_DRIVE_STRENGTH 0x30
- #define IMX6SDL_DRIVE_STRENGTH 0x28
- #ifdef CONFIG_SPL_OS_BOOT
- int spl_start_uboot(void)
- {
- /* Break into full U-Boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
- return 0;
- }
- #endif
- /* configure MX6Q/DUAL mmdc DDR io registers */
- static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
- .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_cas = IMX6DQ_DRIVE_STRENGTH,
- .dram_ras = IMX6DQ_DRIVE_STRENGTH,
- .dram_reset = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
- };
- /* configure MX6Q/DUAL mmdc GRP io registers */
- static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6DQ_DRIVE_STRENGTH,
- .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
- };
- /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
- struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
- .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_cas = IMX6SDL_DRIVE_STRENGTH,
- .dram_ras = IMX6SDL_DRIVE_STRENGTH,
- .dram_reset = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
- };
- /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
- struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
- };
- /* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
- static struct mx6_ddr3_cfg h5t04g63afr = {
- .mem_speed = 800,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1500,
- .trcmin = 5250,
- .trasmin = 3750,
- };
- /* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
- static struct mx6_ddr3_cfg h5tq2g63ffr = {
- .mem_speed = 800,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1500,
- .trcmin = 5250,
- .trasmin = 3750,
- };
- static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpwldectrl1 = 0x00000000,
- .p1_mpwldectrl0 = 0x00000000,
- .p1_mpwldectrl1 = 0x00000000,
- .p0_mpdgctrl0 = 0x032C0340,
- .p0_mpdgctrl1 = 0x03300324,
- .p1_mpdgctrl0 = 0x032C0338,
- .p1_mpdgctrl1 = 0x03300274,
- .p0_mprddlctl = 0x423A383E,
- .p1_mprddlctl = 0x3638323E,
- .p0_mpwrdlctl = 0x363C4640,
- .p1_mpwrdlctl = 0x4034423C,
- };
- /* DDR 32bit */
- static struct mx6_ddr_sysinfo mem_s = {
- .dsize = 1,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 0,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
- };
- static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x001f001f,
- .p0_mpwldectrl1 = 0x001f001f,
- .p1_mpwldectrl0 = 0x001f001f,
- .p1_mpwldectrl1 = 0x001f001f,
- .p0_mpdgctrl0 = 0x420e020e,
- .p0_mpdgctrl1 = 0x02000200,
- .p1_mpdgctrl0 = 0x42020202,
- .p1_mpdgctrl1 = 0x01720172,
- .p0_mprddlctl = 0x494c4f4c,
- .p1_mprddlctl = 0x4a4c4c49,
- .p0_mpwrdlctl = 0x3f3f3133,
- .p1_mpwrdlctl = 0x39373f2e,
- };
- static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
- .p0_mpwldectrl0 = 0x0040003c,
- .p0_mpwldectrl1 = 0x0032003e,
- .p0_mpdgctrl0 = 0x42350231,
- .p0_mpdgctrl1 = 0x021a0218,
- .p0_mprddlctl = 0x4b4b4e49,
- .p0_mpwrdlctl = 0x3f3f3035,
- };
- static void ccgr_init(void)
- {
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF03000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
- }
- static void spl_dram_init(void)
- {
- if (is_mx6solo()) {
- mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
- } else if (is_mx6dl()) {
- mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
- } else if (is_mx6dq()) {
- mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
- mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
- }
- udelay(100);
- }
- void board_init_f(ulong dummy)
- {
- ccgr_init();
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
- gpr_init();
- /* iomux */
- board_early_init_f();
- /* setup GP timer */
- timer_init();
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
- /* DDR initialization */
- spl_dram_init();
- }
- #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
- static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC3_BASE_ADDR},
- };
- static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* SOM MicroSD Card Detect */
- IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- };
- int board_mmc_getcd(struct mmc *mmc)
- {
- return 1;
- }
- int board_mmc_init(bd_t *bis)
- {
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- }
- #endif
- #ifdef CONFIG_SPL_LOAD_FIT
- int board_fit_config_name_match(const char *name)
- {
- if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
- return 0;
- else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
- return 0;
- return -EINVAL;
- }
- #endif
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