pico-imx6.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2014 O.S. Systems Software LTDA.
  5. *
  6. * Author: Fabio Estevam <festevam@gmail.com>
  7. */
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch/mxc_hdmi.h>
  16. #include <asm/mach-imx/video.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/io.h>
  19. #include <linux/sizes.h>
  20. #include <common.h>
  21. #include <miiphy.h>
  22. #include <netdev.h>
  23. #include <phy.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  26. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  27. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  28. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  29. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  30. #define ETH_PHY_RESET IMX_GPIO_NR(1, 26)
  31. #define LVDS0_EN IMX_GPIO_NR(2, 8)
  32. #define LVDS0_BL_EN IMX_GPIO_NR(2, 9)
  33. int dram_init(void)
  34. {
  35. gd->ram_size = imx_ddr_size();
  36. return 0;
  37. }
  38. static iomux_v3_cfg_t const uart1_pads[] = {
  39. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  40. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  41. };
  42. static void setup_iomux_uart(void)
  43. {
  44. SETUP_IOMUX_PADS(uart1_pads);
  45. }
  46. static iomux_v3_cfg_t const lvds_pads[] = {
  47. /* lvds */
  48. IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  49. IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  50. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
  51. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  52. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  53. };
  54. static iomux_v3_cfg_t const enet_pads[] = {
  55. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  56. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  57. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  63. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  65. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72. /* AR8035 PHY Reset */
  73. IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  74. };
  75. static void setup_iomux_enet(void)
  76. {
  77. SETUP_IOMUX_PADS(enet_pads);
  78. /* Reset AR8031 PHY */
  79. gpio_request(ETH_PHY_RESET, "enet_phy_reset");
  80. gpio_direction_output(ETH_PHY_RESET, 0);
  81. udelay(500);
  82. gpio_set_value(ETH_PHY_RESET, 1);
  83. }
  84. #if defined(CONFIG_VIDEO_IPUV3)
  85. static iomux_v3_cfg_t const ft5x06_wvga_pads[] = {
  86. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
  87. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
  88. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
  89. IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
  90. IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
  91. IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
  92. IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
  93. IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
  94. IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
  95. IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
  96. IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
  97. IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
  98. IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
  99. IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
  100. IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
  101. IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
  102. IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
  103. IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
  104. IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
  105. IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
  106. IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
  107. IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
  108. IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
  109. IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
  110. IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
  111. IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
  112. IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
  113. IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
  114. IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
  115. IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
  116. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
  117. };
  118. static void do_enable_hdmi(struct display_info_t const *dev)
  119. {
  120. imx_enable_hdmi_phy();
  121. }
  122. static void enable_lvds(struct display_info_t const *dev)
  123. {
  124. struct iomuxc *iomux = (struct iomuxc *)
  125. IOMUXC_BASE_ADDR;
  126. /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
  127. u32 reg = readl(&iomux->gpr[2]);
  128. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  129. writel(reg, &iomux->gpr[2]);
  130. /* Enable Backlight - use GPIO for Brightness adjustment */
  131. SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
  132. gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable");
  133. gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
  134. gpio_request(IMX_GPIO_NR(2, 8), "brightness");
  135. SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
  136. gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
  137. }
  138. static void enable_ft5x06_wvga(struct display_info_t const *dev)
  139. {
  140. SETUP_IOMUX_PADS(ft5x06_wvga_pads);
  141. gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable");
  142. gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness");
  143. gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
  144. gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
  145. }
  146. struct display_info_t const displays[] = {{
  147. .bus = 1,
  148. .addr = 0x38,
  149. .pixfmt = IPU_PIX_FMT_RGB24,
  150. .detect = NULL,
  151. .enable = enable_ft5x06_wvga,
  152. .mode = {
  153. .name = "FT5x06-WVGA",
  154. .refresh = 60,
  155. .xres = 800,
  156. .yres = 480,
  157. .pixclock = 30303,
  158. .left_margin = 45,
  159. .right_margin = 210,
  160. .upper_margin = 22,
  161. .lower_margin = 22,
  162. .hsync_len = 1,
  163. .vsync_len = 1,
  164. .sync = 0,
  165. .vmode = FB_VMODE_NONINTERLACED
  166. } }, {
  167. .bus = -1,
  168. .addr = 0,
  169. .pixfmt = IPU_PIX_FMT_RGB24,
  170. .detect = NULL,
  171. .enable = enable_lvds,
  172. .mode = {
  173. .name = "hj070na",
  174. .refresh = 60,
  175. .xres = 1024,
  176. .yres = 600,
  177. .pixclock = 15385,
  178. .left_margin = 220,
  179. .right_margin = 40,
  180. .upper_margin = 21,
  181. .lower_margin = 7,
  182. .hsync_len = 60,
  183. .vsync_len = 10,
  184. .sync = FB_SYNC_EXT,
  185. .vmode = FB_VMODE_NONINTERLACED
  186. } }, {
  187. .bus = -1,
  188. .addr = 0,
  189. .pixfmt = IPU_PIX_FMT_RGB24,
  190. .detect = detect_hdmi,
  191. .enable = do_enable_hdmi,
  192. .mode = {
  193. .name = "HDMI",
  194. .refresh = 60,
  195. .xres = 1024,
  196. .yres = 768,
  197. .pixclock = 15385,
  198. .left_margin = 220,
  199. .right_margin = 40,
  200. .upper_margin = 21,
  201. .lower_margin = 7,
  202. .hsync_len = 60,
  203. .vsync_len = 10,
  204. .sync = FB_SYNC_EXT,
  205. .vmode = FB_VMODE_NONINTERLACED
  206. } } };
  207. size_t display_count = ARRAY_SIZE(displays);
  208. static void setup_display(void)
  209. {
  210. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  211. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  212. int reg;
  213. /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
  214. SETUP_IOMUX_PADS(lvds_pads);
  215. gpio_request(LVDS0_EN, "lvds0_enable");
  216. gpio_request(LVDS0_BL_EN, "lvds0_bl_enable");
  217. gpio_direction_output(LVDS0_EN, 1);
  218. gpio_direction_output(LVDS0_BL_EN, 1);
  219. enable_ipu_clock();
  220. imx_setup_hdmi();
  221. reg = __raw_readl(&mxc_ccm->CCGR3);
  222. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
  223. writel(reg, &mxc_ccm->CCGR3);
  224. /* set LDB0, LDB1 clk select to 011/011 */
  225. reg = readl(&mxc_ccm->cs2cdr);
  226. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  227. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  228. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  229. | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  230. writel(reg, &mxc_ccm->cs2cdr);
  231. reg = readl(&mxc_ccm->cscmr2);
  232. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
  233. writel(reg, &mxc_ccm->cscmr2);
  234. reg = readl(&mxc_ccm->chsccdr);
  235. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  236. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  237. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  238. << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  239. writel(reg, &mxc_ccm->chsccdr);
  240. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  241. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
  242. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  243. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  244. | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
  245. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  246. | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  247. | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
  248. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  249. writel(reg, &iomux->gpr[2]);
  250. reg = readl(&iomux->gpr[3]);
  251. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  252. | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  253. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  254. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  255. writel(reg, &iomux->gpr[3]);
  256. }
  257. #endif /* CONFIG_VIDEO_IPUV3 */
  258. int board_early_init_f(void)
  259. {
  260. setup_iomux_uart();
  261. #if defined(CONFIG_VIDEO_IPUV3)
  262. setup_display();
  263. #endif
  264. return 0;
  265. }
  266. int board_eth_init(bd_t *bis)
  267. {
  268. setup_iomux_enet();
  269. return cpu_eth_init(bis);
  270. }
  271. int board_phy_config(struct phy_device *phydev)
  272. {
  273. unsigned short val;
  274. /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
  275. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  276. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  277. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  278. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  279. val &= 0xffe7;
  280. val |= 0x18;
  281. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  282. /* introduce tx clock delay */
  283. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  284. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  285. val |= 0x0100;
  286. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  287. if (phydev->drv->config)
  288. phydev->drv->config(phydev);
  289. return 0;
  290. }
  291. int overwrite_console(void)
  292. {
  293. return 1;
  294. }
  295. int board_late_init(void)
  296. {
  297. if (is_mx6dq())
  298. env_set("board_rev", "MX6Q");
  299. else
  300. env_set("board_rev", "MX6DL");
  301. return 0;
  302. }
  303. int board_init(void)
  304. {
  305. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  306. return 0;
  307. }
  308. int checkboard(void)
  309. {
  310. puts("Board: PICO-IMX6\n");
  311. return 0;
  312. }