board.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TCL SL50 board
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <serial.h>
  14. #include <spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/omap.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/mmc_host_def.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/mem.h>
  24. #include <asm/io.h>
  25. #include <asm/emif.h>
  26. #include <asm/gpio.h>
  27. #include <i2c.h>
  28. #include <miiphy.h>
  29. #include <cpsw.h>
  30. #include <power/tps65217.h>
  31. #include <power/tps65910.h>
  32. #include <env_internal.h>
  33. #include <watchdog.h>
  34. #include "board.h"
  35. DECLARE_GLOBAL_DATA_PTR;
  36. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  37. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  38. static const struct ddr_data ddr3_sl50_data = {
  39. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  40. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  41. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  42. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  43. };
  44. static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
  45. .cmd0csratio = MT41K256M16HA125E_RATIO,
  46. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  47. .cmd1csratio = MT41K256M16HA125E_RATIO,
  48. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  49. .cmd2csratio = MT41K256M16HA125E_RATIO,
  50. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  51. };
  52. static struct emif_regs ddr3_sl50_emif_reg_data = {
  53. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  54. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  55. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  56. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  57. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  58. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  59. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  60. };
  61. #ifdef CONFIG_SPL_OS_BOOT
  62. int spl_start_uboot(void)
  63. {
  64. /* break into full u-boot on 'c' */
  65. if (serial_tstc() && serial_getc() == 'c')
  66. return 1;
  67. #ifdef CONFIG_SPL_ENV_SUPPORT
  68. env_init();
  69. env_load();
  70. if (env_get_yesno("boot_os") != 1)
  71. return 1;
  72. #endif
  73. return 0;
  74. }
  75. #endif
  76. #define OSC (V_OSCK/1000000)
  77. const struct dpll_params dpll_ddr_sl50 = {
  78. 400, OSC-1, 1, -1, -1, -1, -1};
  79. void am33xx_spl_board_init(void)
  80. {
  81. int mpu_vdd;
  82. /* Get the frequency */
  83. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  84. /* BeagleBone PMIC Code */
  85. int usb_cur_lim;
  86. if (i2c_probe(TPS65217_CHIP_PM))
  87. return;
  88. /*
  89. * Increase USB current limit to 1300mA or 1800mA and set
  90. * the MPU voltage controller as needed.
  91. */
  92. if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  93. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  94. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  95. } else {
  96. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  97. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  98. }
  99. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  100. TPS65217_POWER_PATH,
  101. usb_cur_lim,
  102. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  103. puts("tps65217_reg_write failure\n");
  104. /* Set DCDC3 (CORE) voltage to 1.125V */
  105. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  106. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  107. puts("tps65217_voltage_update failure\n");
  108. return;
  109. }
  110. /* Set CORE Frequencies to OPP100 */
  111. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  112. /* Set DCDC2 (MPU) voltage */
  113. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  114. puts("tps65217_voltage_update failure\n");
  115. return;
  116. }
  117. /*
  118. * Set LDO3 to 1.8V and LDO4 to 3.3V
  119. */
  120. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  121. TPS65217_DEFLS1,
  122. TPS65217_LDO_VOLTAGE_OUT_1_8,
  123. TPS65217_LDO_MASK))
  124. puts("tps65217_reg_write failure\n");
  125. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  126. TPS65217_DEFLS2,
  127. TPS65217_LDO_VOLTAGE_OUT_3_3,
  128. TPS65217_LDO_MASK))
  129. puts("tps65217_reg_write failure\n");
  130. /* Set MPU Frequency to what we detected now that voltages are set */
  131. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  132. }
  133. const struct dpll_params *get_dpll_ddr_params(void)
  134. {
  135. enable_i2c0_pin_mux();
  136. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  137. return &dpll_ddr_sl50;
  138. }
  139. void set_uart_mux_conf(void)
  140. {
  141. #if CONFIG_CONS_INDEX == 1
  142. enable_uart0_pin_mux();
  143. #elif CONFIG_CONS_INDEX == 2
  144. enable_uart1_pin_mux();
  145. #elif CONFIG_CONS_INDEX == 3
  146. enable_uart2_pin_mux();
  147. #elif CONFIG_CONS_INDEX == 4
  148. enable_uart3_pin_mux();
  149. #elif CONFIG_CONS_INDEX == 5
  150. enable_uart4_pin_mux();
  151. #elif CONFIG_CONS_INDEX == 6
  152. enable_uart5_pin_mux();
  153. #endif
  154. }
  155. void set_mux_conf_regs(void)
  156. {
  157. enable_board_pin_mux();
  158. }
  159. const struct ctrl_ioregs ioregs_evmsk = {
  160. .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  161. .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  162. .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
  163. .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  164. .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  165. };
  166. const struct ctrl_ioregs ioregs_bonelt = {
  167. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  168. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  169. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  170. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  171. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  172. };
  173. const struct ctrl_ioregs ioregs_evm15 = {
  174. .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  175. .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  176. .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  177. .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  178. .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  179. };
  180. const struct ctrl_ioregs ioregs = {
  181. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  182. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  183. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  184. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  185. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  186. };
  187. void sdram_init(void)
  188. {
  189. config_ddr(400, &ioregs_bonelt,
  190. &ddr3_sl50_data,
  191. &ddr3_sl50_cmd_ctrl_data,
  192. &ddr3_sl50_emif_reg_data, 0);
  193. }
  194. #endif
  195. /*
  196. * Basic board specific setup. Pinmux has been handled already.
  197. */
  198. int board_init(void)
  199. {
  200. #if defined(CONFIG_HW_WATCHDOG)
  201. hw_watchdog_init();
  202. #endif
  203. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  204. return 0;
  205. }
  206. #ifdef CONFIG_BOARD_LATE_INIT
  207. int board_late_init(void)
  208. {
  209. return 0;
  210. }
  211. #endif
  212. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  213. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  214. static void cpsw_control(int enabled)
  215. {
  216. /* VTP can be added here */
  217. return;
  218. }
  219. static struct cpsw_slave_data cpsw_slaves[] = {
  220. {
  221. .slave_reg_ofs = 0x208,
  222. .sliver_reg_ofs = 0xd80,
  223. .phy_addr = 0,
  224. },
  225. {
  226. .slave_reg_ofs = 0x308,
  227. .sliver_reg_ofs = 0xdc0,
  228. .phy_addr = 1,
  229. },
  230. };
  231. static struct cpsw_platform_data cpsw_data = {
  232. .mdio_base = CPSW_MDIO_BASE,
  233. .cpsw_base = CPSW_BASE,
  234. .mdio_div = 0xff,
  235. .channels = 8,
  236. .cpdma_reg_ofs = 0x800,
  237. .slaves = 1,
  238. .slave_data = cpsw_slaves,
  239. .ale_reg_ofs = 0xd00,
  240. .ale_entries = 1024,
  241. .host_port_reg_ofs = 0x108,
  242. .hw_stats_reg_ofs = 0x900,
  243. .bd_ram_ofs = 0x2000,
  244. .mac_control = (1 << 5),
  245. .control = cpsw_control,
  246. .host_port_num = 0,
  247. .version = CPSW_CTRL_VERSION_2,
  248. };
  249. #endif
  250. /*
  251. * This function will:
  252. * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
  253. * in the environment
  254. * Perform fixups to the PHY present on certain boards. We only need this
  255. * function in:
  256. * - SPL with either CPSW or USB ethernet support
  257. * - Full U-Boot, with either CPSW or USB ethernet
  258. * Build in only these cases to avoid warnings about unused variables
  259. * when we build an SPL that has neither option but full U-Boot will.
  260. */
  261. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
  262. && defined(CONFIG_SPL_BUILD)) || \
  263. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  264. defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
  265. !defined(CONFIG_SPL_BUILD))
  266. int board_eth_init(bd_t *bis)
  267. {
  268. int rv, n = 0;
  269. uint8_t mac_addr[6];
  270. uint32_t mac_hi, mac_lo;
  271. /* try reading mac address from efuse */
  272. mac_lo = readl(&cdev->macid0l);
  273. mac_hi = readl(&cdev->macid0h);
  274. mac_addr[0] = mac_hi & 0xFF;
  275. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  276. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  277. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  278. mac_addr[4] = mac_lo & 0xFF;
  279. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  280. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  281. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  282. if (!env_get("ethaddr")) {
  283. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  284. if (is_valid_ethaddr(mac_addr))
  285. eth_env_set_enetaddr("ethaddr", mac_addr);
  286. }
  287. #ifdef CONFIG_DRIVER_TI_CPSW
  288. mac_lo = readl(&cdev->macid1l);
  289. mac_hi = readl(&cdev->macid1h);
  290. mac_addr[0] = mac_hi & 0xFF;
  291. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  292. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  293. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  294. mac_addr[4] = mac_lo & 0xFF;
  295. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  296. if (!env_get("eth1addr")) {
  297. if (is_valid_ethaddr(mac_addr))
  298. eth_env_set_enetaddr("eth1addr", mac_addr);
  299. }
  300. writel(MII_MODE_ENABLE, &cdev->miisel);
  301. cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
  302. PHY_INTERFACE_MODE_MII;
  303. rv = cpsw_register(&cpsw_data);
  304. if (rv < 0)
  305. printf("Error %d registering CPSW switch\n", rv);
  306. else
  307. n += rv;
  308. #endif
  309. /*
  310. *
  311. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  312. * operating points. So we must set the TX clock delay feature
  313. * in the AR8051 PHY. Since we only support a single ethernet
  314. * device in U-Boot, we only do this for the first instance.
  315. */
  316. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  317. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  318. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  319. #define AR8051_RGMII_TX_CLK_DLY 0x100
  320. #endif
  321. #if defined(CONFIG_USB_ETHER) && \
  322. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
  323. if (is_valid_ether_addr(mac_addr))
  324. eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
  325. rv = usb_eth_initialize(bis);
  326. if (rv < 0)
  327. printf("Error %d registering USB_ETHER\n", rv);
  328. else
  329. n += rv;
  330. #endif
  331. return n;
  332. }
  333. #endif