tbs2910.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Soeren Moch <smoch@web.de>
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/imx-regs.h>
  7. #include <asm/arch/iomux.h>
  8. #include <asm/arch/mx6-pins.h>
  9. #include <linux/errno.h>
  10. #include <asm/gpio.h>
  11. #include <asm/mach-imx/iomux-v3.h>
  12. #include <asm/mach-imx/boot_mode.h>
  13. #include <asm/mach-imx/video.h>
  14. #include <mmc.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <asm/arch/mxc_hdmi.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/sys_proto.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  22. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  23. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  24. static iomux_v3_cfg_t const uart1_pads[] = {
  25. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  26. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  27. };
  28. static iomux_v3_cfg_t const uart2_pads[] = {
  29. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  30. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  31. };
  32. int dram_init(void)
  33. {
  34. gd->ram_size = 2048ul * 1024 * 1024;
  35. return 0;
  36. }
  37. static void setup_iomux_uart(void)
  38. {
  39. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  40. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  41. }
  42. #ifdef CONFIG_FSL_ESDHC_IMX
  43. /* set environment device to boot device when booting from SD */
  44. int board_mmc_get_env_dev(int devno)
  45. {
  46. return devno - 1;
  47. }
  48. int board_mmc_get_env_part(int devno)
  49. {
  50. return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
  51. }
  52. #endif /* CONFIG_FSL_ESDHC_IMX */
  53. #ifdef CONFIG_VIDEO_IPUV3
  54. static void do_enable_hdmi(struct display_info_t const *dev)
  55. {
  56. imx_enable_hdmi_phy();
  57. }
  58. struct display_info_t const displays[] = {{
  59. .bus = -1,
  60. .addr = 0,
  61. .pixfmt = IPU_PIX_FMT_RGB24,
  62. .detect = detect_hdmi,
  63. .enable = do_enable_hdmi,
  64. .mode = {
  65. .name = "HDMI",
  66. /* 1024x768@60Hz (VESA)*/
  67. .refresh = 60,
  68. .xres = 1024,
  69. .yres = 768,
  70. .pixclock = 15384,
  71. .left_margin = 160,
  72. .right_margin = 24,
  73. .upper_margin = 29,
  74. .lower_margin = 3,
  75. .hsync_len = 136,
  76. .vsync_len = 6,
  77. .sync = FB_SYNC_EXT,
  78. .vmode = FB_VMODE_NONINTERLACED
  79. } } };
  80. size_t display_count = ARRAY_SIZE(displays);
  81. static void setup_display(void)
  82. {
  83. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  84. int reg;
  85. s32 timeout = 100000;
  86. enable_ipu_clock();
  87. imx_setup_hdmi();
  88. /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
  89. reg = readl(&ccm->analog_pll_video);
  90. reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
  91. writel(reg, &ccm->analog_pll_video);
  92. reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  93. reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
  94. reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  95. reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
  96. writel(reg, &ccm->analog_pll_video);
  97. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  98. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  99. reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  100. writel(reg, &ccm->analog_pll_video);
  101. while (timeout--)
  102. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  103. break;
  104. if (timeout < 0)
  105. printf("Warning: video pll lock timeout!\n");
  106. reg = readl(&ccm->analog_pll_video);
  107. reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
  108. reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
  109. writel(reg, &ccm->analog_pll_video);
  110. /* gate ipu1_di0_clk */
  111. reg = readl(&ccm->CCGR3);
  112. reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
  113. writel(reg, &ccm->CCGR3);
  114. /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
  115. reg = readl(&ccm->chsccdr);
  116. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
  117. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
  118. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  119. reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
  120. (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
  121. (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  122. writel(reg, &ccm->chsccdr);
  123. /* enable ipu1_di0_clk */
  124. reg = readl(&ccm->CCGR3);
  125. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  126. writel(reg, &ccm->CCGR3);
  127. }
  128. #endif /* CONFIG_VIDEO_IPUV3 */
  129. int board_early_init_f(void)
  130. {
  131. setup_iomux_uart();
  132. return 0;
  133. }
  134. #ifdef CONFIG_CMD_BMODE
  135. static const struct boot_mode board_boot_modes[] = {
  136. /* 4 bit bus width */
  137. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  138. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  139. /* 8 bit bus width */
  140. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  141. {NULL, 0},
  142. };
  143. #endif
  144. int board_init(void)
  145. {
  146. /* address of boot parameters */
  147. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  148. #ifdef CONFIG_VIDEO_IPUV3
  149. setup_display();
  150. #endif
  151. #ifdef CONFIG_CMD_BMODE
  152. add_board_boot_modes(board_boot_modes);
  153. #endif
  154. return 0;
  155. }