amcore.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Sysam AMCORE (MCF5307 based) board
  4. *
  5. * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
  6. *
  7. * This file copies memory testdram() from sandburst/common/sb_common.c
  8. */
  9. #include <common.h>
  10. #include <asm/immap.h>
  11. #include <asm/io.h>
  12. #include <dm.h>
  13. #include <dm/platform_data/serial_coldfire.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. void init_lcd(void)
  16. {
  17. /* setup for possible K0108 lcd connected on the parallel port */
  18. sim_t *sim = (sim_t *)(MMAP_SIM);
  19. out_be16(&sim->par, 0x300);
  20. gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
  21. out_be16(&gpio->paddr, 0xfcff);
  22. out_be16(&gpio->padat, 0x0c00);
  23. }
  24. int checkboard(void)
  25. {
  26. puts("Board: ");
  27. puts("AMCORE v.001(alpha)\n");
  28. init_lcd();
  29. return 0;
  30. }
  31. /*
  32. * in dram_init we are here executing from flash
  33. * case 1:
  34. * is with no ACR/flash cache enabled
  35. * nop = 40ns (scope measured)
  36. */
  37. void fudelay(int usec)
  38. {
  39. while (usec--)
  40. asm volatile ("nop");
  41. }
  42. int dram_init(void)
  43. {
  44. u32 dramsize, RC;
  45. sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
  46. /*
  47. * SDRAM MT48LC4M32B2 details
  48. * Memory block 0: 16 MB of SDRAM at address $00000000
  49. * Port size: 32-bit port
  50. *
  51. * Memory block 0 wired as follows:
  52. * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
  53. * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
  54. *
  55. * Ensure that there is a delay of at least 100 microseconds from
  56. * processor reset to the following code so that the SDRAM is ready
  57. * for commands.
  58. */
  59. fudelay(100);
  60. /*
  61. * DCR
  62. * set proper RC as per specification
  63. */
  64. RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
  65. RC = (RC * 15) >> 4;
  66. /* 0x8000 is the faster option */
  67. out_be16(&dc->dcr, 0x8200 | RC);
  68. /*
  69. * DACR0, page mode continuous, CMD on A20 0x0300
  70. */
  71. out_be32(&dc->dacr0, 0x00003304);
  72. dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
  73. out_be32(&dc->dmr0, dramsize|1);
  74. /* issue a PRECHARGE ALL */
  75. out_be32(&dc->dacr0, 0x0000330c);
  76. out_be32((u32 *)0x00000004, 0xbeaddeed);
  77. /* issue AUTOREFRESH */
  78. out_be32(&dc->dacr0, 0x0000b304);
  79. /* let refresh occur */
  80. fudelay(1);
  81. out_be32(&dc->dacr0, 0x0000b344);
  82. out_be32((u32 *)0x00000c00, 0xbeaddeed);
  83. gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
  84. CONFIG_SYS_SDRAM_SIZE);
  85. return 0;
  86. }
  87. static struct coldfire_serial_platdata mcf5307_serial_plat = {
  88. .base = CONFIG_SYS_UART_BASE,
  89. .port = 0,
  90. .baudrate = CONFIG_BAUDRATE,
  91. };
  92. U_BOOT_DEVICE(coldfire_serial) = {
  93. .name = "serial_coldfire",
  94. .platdata = &mcf5307_serial_plat,
  95. };