iot_devkit.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <dwmmc.h>
  8. #include <linux/libfdt.h>
  9. #include <fdtdec.h>
  10. #include <asm/arcregs.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #define SYSCON_BASE 0xf000a000
  13. #define AHBCKDIV (void *)(SYSCON_BASE + 0x04)
  14. #define APBCKDIV (void *)(SYSCON_BASE + 0x08)
  15. #define APBCKEN (void *)(SYSCON_BASE + 0x0C)
  16. #define RESET_REG (void *)(SYSCON_BASE + 0x18)
  17. #define CLKSEL (void *)(SYSCON_BASE + 0x24)
  18. #define CLKSTAT (void *)(SYSCON_BASE + 0x28)
  19. #define PLLCON (void *)(SYSCON_BASE + 0x2C)
  20. #define APBCKSEL (void *)(SYSCON_BASE + 0x30)
  21. #define AHBCKEN (void *)(SYSCON_BASE + 0x34)
  22. #define USBPHY_PLL (void *)(SYSCON_BASE + 0x78)
  23. #define USBCFG (void *)(SYSCON_BASE + 0x7c)
  24. #define PLL_MASK_0 0xffcfffff
  25. #define PLL_MASK_1 0xffcfff00
  26. #define PLL_MASK_2 0xfbcfff00
  27. #define CLKSEL_DEFAULT 0x5a690000
  28. static int set_cpu_freq(unsigned int clk)
  29. {
  30. clk /= 1000000;
  31. /* Set clk to ext Xtal (LSN value 0) */
  32. writel(CLKSEL_DEFAULT, CLKSEL);
  33. switch (clk) {
  34. case 16:
  35. /* Bypass mode */
  36. return 0;
  37. case 50:
  38. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  39. /* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
  40. writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON);
  41. /* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
  42. writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON);
  43. break;
  44. case 72:
  45. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  46. /* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
  47. writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON);
  48. /* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
  49. writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON);
  50. break;
  51. case 100:
  52. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  53. /* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
  54. writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON);
  55. /* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
  56. writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON);
  57. break;
  58. case 136:
  59. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  60. /* pll_off=1, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
  61. writel((readl(PLLCON) & PLL_MASK_1) | 0x100111, PLLCON);
  62. /* pll_off=0, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
  63. writel((readl(PLLCON) & PLL_MASK_2) | 0x100111, PLLCON);
  64. break;
  65. case 144:
  66. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  67. /* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
  68. writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON);
  69. /* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
  70. writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON);
  71. break;
  72. default:
  73. return -EINVAL;
  74. }
  75. while (!(readl(CLKSTAT) & 0x4))
  76. ;
  77. /* Set clk from PLL on bus (LSN = 1) */
  78. writel(CLKSEL_DEFAULT | BIT(0), CLKSEL);
  79. return 0;
  80. }
  81. extern u8 __rom_end[];
  82. extern u8 __ram_start[];
  83. extern u8 __ram_end[];
  84. /*
  85. * Use mach_cpu_init() for .data section copy as board_early_init_f() will be
  86. * too late: initf_dm() will use a value of "av_" variable from not yet
  87. * initialized (by copy) area.
  88. */
  89. int mach_cpu_init(void)
  90. {
  91. int offset;
  92. /* Don't relocate U-Boot */
  93. gd->flags |= GD_FLG_SKIP_RELOC;
  94. /* Copy data from ROM to RAM */
  95. u8 *src = __rom_end;
  96. u8 *dst = __ram_start;
  97. while (dst < __ram_end)
  98. *dst++ = *src++;
  99. /* Enable debug uart */
  100. #define DEBUG_UART_BASE 0x80014000
  101. #define DEBUG_UART_DLF_OFFSET 0xc0
  102. write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1);
  103. offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk");
  104. if (offset < 0)
  105. return offset;
  106. gd->cpu_clk = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0);
  107. if (!gd->cpu_clk)
  108. return -EINVAL;
  109. /* If CPU freq > 100 MHz, divide eFLASH clock by 2 */
  110. if (gd->cpu_clk > 100000000) {
  111. u32 reg = readl(AHBCKDIV);
  112. reg &= ~(0xF << 8);
  113. reg |= 2 << 8;
  114. writel(reg, AHBCKDIV);
  115. }
  116. return set_cpu_freq(gd->cpu_clk);
  117. }
  118. #define IOTDK_RESET_SEQ 0x55AA6699
  119. void reset_cpu(ulong addr)
  120. {
  121. writel(IOTDK_RESET_SEQ, RESET_REG);
  122. }
  123. int checkboard(void)
  124. {
  125. puts("Board: Synopsys IoT Development Kit\n");
  126. return 0;
  127. };