hsdk.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
  4. * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  5. */
  6. #include <common.h>
  7. #include <config.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <init.h>
  11. #include <irq_func.h>
  12. #include <linux/printk.h>
  13. #include <linux/kernel.h>
  14. #include <linux/io.h>
  15. #include <asm/arcregs.h>
  16. #include <fdt_support.h>
  17. #include <dwmmc.h>
  18. #include <malloc.h>
  19. #include <usb.h>
  20. #include "clk-lib.h"
  21. #include "env-lib.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define ALL_CPU_MASK GENMASK(NR_CPUS - 1, 0)
  24. #define MASTER_CPU_ID 0
  25. #define APERTURE_SHIFT 28
  26. #define NO_CCM 0x10
  27. #define SLAVE_CPU_READY 0x12345678
  28. #define BOOTSTAGE_1 1 /* after SP, FP setup, before HW init */
  29. #define BOOTSTAGE_2 2 /* after HW init, before self halt */
  30. #define BOOTSTAGE_3 3 /* after self halt */
  31. #define BOOTSTAGE_4 4 /* before app launch */
  32. #define BOOTSTAGE_5 5 /* after app launch, unreachable */
  33. #define RESET_VECTOR_ADDR 0x0
  34. #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
  35. #define CREG_CPU_START (CREG_BASE + 0x400)
  36. #define CREG_CPU_START_MASK 0xF
  37. #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
  38. #define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
  39. #define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
  40. /* Uncached access macros */
  41. #define arc_read_uncached_32(ptr) \
  42. ({ \
  43. unsigned int __ret; \
  44. __asm__ __volatile__( \
  45. " ld.di %0, [%1] \n" \
  46. : "=r"(__ret) \
  47. : "r"(ptr)); \
  48. __ret; \
  49. })
  50. #define arc_write_uncached_32(ptr, data)\
  51. ({ \
  52. __asm__ __volatile__( \
  53. " st.di %0, [%1] \n" \
  54. : \
  55. : "r"(data), "r"(ptr)); \
  56. })
  57. struct hsdk_env_core_ctl {
  58. u32_env entry[NR_CPUS];
  59. u32_env iccm[NR_CPUS];
  60. u32_env dccm[NR_CPUS];
  61. };
  62. struct hsdk_env_common_ctl {
  63. bool halt_on_boot;
  64. u32_env core_mask;
  65. u32_env cpu_freq;
  66. u32_env axi_freq;
  67. u32_env tun_freq;
  68. u32_env nvlim;
  69. u32_env icache;
  70. u32_env dcache;
  71. };
  72. /*
  73. * Uncached cross-cpu structure. All CPUs must access to this structure fields
  74. * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which
  75. * implement ld.di / st.di instructions). Simultaneous cached and uncached
  76. * access to this area will lead to data loss.
  77. * We flush all data caches in board_early_init_r() as we don't want to have
  78. * any dirty line in L1d$ or SL$ in this area.
  79. */
  80. struct hsdk_cross_cpu {
  81. /* slave CPU ready flag */
  82. u32 ready_flag;
  83. /* address of the area, which can be used for stack by slave CPU */
  84. u32 stack_ptr;
  85. /* slave CPU status - bootstage number */
  86. s32 status[NR_CPUS];
  87. /*
  88. * Slave CPU data - it is copy of corresponding fields in
  89. * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are
  90. * required for slave CPUs initialization.
  91. * This fields can be populated by copying from hsdk_env_core_ctl
  92. * and hsdk_env_common_ctl structures with sync_cross_cpu_data()
  93. * function.
  94. */
  95. u32 entry[NR_CPUS];
  96. u32 iccm[NR_CPUS];
  97. u32 dccm[NR_CPUS];
  98. u32 core_mask;
  99. u32 icache;
  100. u32 dcache;
  101. u8 cache_padding[ARCH_DMA_MINALIGN];
  102. } __aligned(ARCH_DMA_MINALIGN);
  103. /* Place for slave CPUs temporary stack */
  104. static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN);
  105. static struct hsdk_env_common_ctl env_common = {};
  106. static struct hsdk_env_core_ctl env_core = {};
  107. static struct hsdk_cross_cpu cross_cpu_data;
  108. static const struct env_map_common env_map_common[] = {
  109. { "core_mask", ENV_HEX, true, 0x1, 0xF, &env_common.core_mask },
  110. { "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim },
  111. { "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache },
  112. { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
  113. {}
  114. };
  115. static const struct env_map_common env_map_clock[] = {
  116. { "cpu_freq", ENV_DEC, false, 100, 1000, &env_common.cpu_freq },
  117. { "axi_freq", ENV_DEC, false, 200, 800, &env_common.axi_freq },
  118. { "tun_freq", ENV_DEC, false, 0, 150, &env_common.tun_freq },
  119. {}
  120. };
  121. static const struct env_map_percpu env_map_core[] = {
  122. { "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm },
  123. { "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm },
  124. {}
  125. };
  126. static const struct env_map_common env_map_mask[] = {
  127. { "core_mask", ENV_HEX, false, 0x1, 0xF, &env_common.core_mask },
  128. {}
  129. };
  130. static const struct env_map_percpu env_map_go[] = {
  131. { "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry },
  132. {}
  133. };
  134. static void sync_cross_cpu_data(void)
  135. {
  136. u32 value;
  137. for (u32 i = 0; i < NR_CPUS; i++) {
  138. value = env_core.entry[i].val;
  139. arc_write_uncached_32(&cross_cpu_data.entry[i], value);
  140. }
  141. for (u32 i = 0; i < NR_CPUS; i++) {
  142. value = env_core.iccm[i].val;
  143. arc_write_uncached_32(&cross_cpu_data.iccm[i], value);
  144. }
  145. for (u32 i = 0; i < NR_CPUS; i++) {
  146. value = env_core.dccm[i].val;
  147. arc_write_uncached_32(&cross_cpu_data.dccm[i], value);
  148. }
  149. value = env_common.core_mask.val;
  150. arc_write_uncached_32(&cross_cpu_data.core_mask, value);
  151. value = env_common.icache.val;
  152. arc_write_uncached_32(&cross_cpu_data.icache, value);
  153. value = env_common.dcache.val;
  154. arc_write_uncached_32(&cross_cpu_data.dcache, value);
  155. }
  156. /* Can be used only on master CPU */
  157. static bool is_cpu_used(u32 cpu_id)
  158. {
  159. return !!(env_common.core_mask.val & BIT(cpu_id));
  160. }
  161. /* TODO: add ICCM BCR and DCCM BCR runtime check */
  162. static void init_slave_cpu_func(u32 core)
  163. {
  164. u32 val;
  165. /* Remap ICCM to another memory region if it exists */
  166. val = arc_read_uncached_32(&cross_cpu_data.iccm[core]);
  167. if (val != NO_CCM)
  168. write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT);
  169. /* Remap DCCM to another memory region if it exists */
  170. val = arc_read_uncached_32(&cross_cpu_data.dccm[core]);
  171. if (val != NO_CCM)
  172. write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT);
  173. if (arc_read_uncached_32(&cross_cpu_data.icache))
  174. icache_enable();
  175. else
  176. icache_disable();
  177. if (arc_read_uncached_32(&cross_cpu_data.dcache))
  178. dcache_enable();
  179. else
  180. dcache_disable();
  181. }
  182. static void init_cluster_nvlim(void)
  183. {
  184. u32 val = env_common.nvlim.val << APERTURE_SHIFT;
  185. flush_dcache_all();
  186. write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
  187. write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
  188. flush_n_invalidate_dcache_all();
  189. }
  190. static void init_master_icache(void)
  191. {
  192. if (icache_status()) {
  193. /* I$ is enabled - we need to disable it */
  194. if (!env_common.icache.val)
  195. icache_disable();
  196. } else {
  197. /* I$ is disabled - we need to enable it */
  198. if (env_common.icache.val) {
  199. icache_enable();
  200. /* invalidate I$ right after enable */
  201. invalidate_icache_all();
  202. }
  203. }
  204. }
  205. static void init_master_dcache(void)
  206. {
  207. if (dcache_status()) {
  208. /* D$ is enabled - we need to disable it */
  209. if (!env_common.dcache.val)
  210. dcache_disable();
  211. } else {
  212. /* D$ is disabled - we need to enable it */
  213. if (env_common.dcache.val)
  214. dcache_enable();
  215. /* TODO: probably we need ti invalidate D$ right after enable */
  216. }
  217. }
  218. static int cleanup_before_go(void)
  219. {
  220. disable_interrupts();
  221. sync_n_cleanup_cache_all();
  222. return 0;
  223. }
  224. void slave_cpu_set_boot_addr(u32 addr)
  225. {
  226. /* All cores have reset vector pointing to 0 */
  227. writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
  228. /* Make sure other cores see written value in memory */
  229. sync_n_cleanup_cache_all();
  230. }
  231. static inline void halt_this_cpu(void)
  232. {
  233. __builtin_arc_flag(1);
  234. }
  235. static void smp_kick_cpu_x(u32 cpu_id)
  236. {
  237. int cmd = readl((void __iomem *)CREG_CPU_START);
  238. if (cpu_id > NR_CPUS)
  239. return;
  240. cmd &= ~CREG_CPU_START_MASK;
  241. cmd |= (1 << cpu_id);
  242. writel(cmd, (void __iomem *)CREG_CPU_START);
  243. }
  244. static u32 prepare_cpu_ctart_reg(void)
  245. {
  246. int cmd = readl((void __iomem *)CREG_CPU_START);
  247. cmd &= ~CREG_CPU_START_MASK;
  248. return cmd | env_common.core_mask.val;
  249. }
  250. /* slave CPU entry for configuration */
  251. __attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void)
  252. {
  253. __asm__ __volatile__(
  254. "ld.di r8, [%0]\n"
  255. "mov %%sp, r8\n"
  256. "mov %%fp, %%sp\n"
  257. : /* no output */
  258. : "r" (&cross_cpu_data.stack_ptr));
  259. invalidate_icache_all();
  260. arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1);
  261. init_slave_cpu_func(CPU_ID_GET());
  262. arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY);
  263. arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2);
  264. /* Halt the processor until the master kick us again */
  265. halt_this_cpu();
  266. /*
  267. * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
  268. * cores but we leave them for gebug purposes.
  269. */
  270. __builtin_arc_nop();
  271. __builtin_arc_nop();
  272. __builtin_arc_nop();
  273. arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3);
  274. /* get the updated entry - invalidate i$ */
  275. invalidate_icache_all();
  276. arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4);
  277. /* Run our program */
  278. ((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))();
  279. /* This bootstage is unreachable as we don't return from app we launch */
  280. arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5);
  281. /* Something went terribly wrong */
  282. while (true)
  283. halt_this_cpu();
  284. }
  285. static void clear_cross_cpu_data(void)
  286. {
  287. arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
  288. arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0);
  289. for (u32 i = 0; i < NR_CPUS; i++)
  290. arc_write_uncached_32(&cross_cpu_data.status[i], 0);
  291. }
  292. static noinline void do_init_slave_cpu(u32 cpu_id)
  293. {
  294. /* attempts number for check clave CPU ready_flag */
  295. u32 attempts = 100;
  296. u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id));
  297. if (cpu_id >= NR_CPUS)
  298. return;
  299. arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
  300. /* Use global unique place for each slave cpu stack */
  301. arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr);
  302. debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack);
  303. debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr);
  304. slave_cpu_set_boot_addr((u32)hsdk_core_init_f);
  305. smp_kick_cpu_x(cpu_id);
  306. debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id,
  307. arc_read_uncached_32(&cross_cpu_data.ready_flag));
  308. while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--)
  309. mdelay(10);
  310. /* Just to be sure that slave cpu is halted after it set ready_flag */
  311. mdelay(20);
  312. /*
  313. * Only print error here if we reach timeout as there is no option to
  314. * halt slave cpu (or check that slave cpu is halted)
  315. */
  316. if (!attempts)
  317. pr_err("CPU %u is not responding after init!\n", cpu_id);
  318. /* Check current stage of slave cpu */
  319. if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2)
  320. pr_err("CPU %u status is unexpected: %d\n", cpu_id,
  321. arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
  322. debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id,
  323. arc_read_uncached_32(&cross_cpu_data.ready_flag));
  324. debug("CPU %u: status: %d [after timeout]\n", cpu_id,
  325. arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
  326. }
  327. static void do_init_slave_cpus(void)
  328. {
  329. clear_cross_cpu_data();
  330. sync_cross_cpu_data();
  331. debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data);
  332. for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++)
  333. if (is_cpu_used(i))
  334. do_init_slave_cpu(i);
  335. }
  336. static void do_init_master_cpu(void)
  337. {
  338. /*
  339. * Setup master caches even if master isn't used as we want to use
  340. * same cache configuration on all running CPUs
  341. */
  342. init_master_icache();
  343. init_master_dcache();
  344. }
  345. enum hsdk_axi_masters {
  346. M_HS_CORE = 0,
  347. M_HS_RTT,
  348. M_AXI_TUN,
  349. M_HDMI_VIDEO,
  350. M_HDMI_AUDIO,
  351. M_USB_HOST,
  352. M_ETHERNET,
  353. M_SDIO,
  354. M_GPU,
  355. M_DMAC_0,
  356. M_DMAC_1,
  357. M_DVFS
  358. };
  359. #define UPDATE_VAL 1
  360. /*
  361. * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
  362. * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
  363. * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
  364. * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
  365. * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
  366. * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
  367. * 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
  368. * 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
  369. * 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
  370. * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
  371. * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
  372. * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
  373. * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
  374. *
  375. * Please read ARC HS Development IC Specification, section 17.2 for more
  376. * information about apertures configuration.
  377. * NOTE: we intentionally modify default settings in U-boot. Default settings
  378. * are specified in "Table 111 CREG Address Decoder register reset values".
  379. */
  380. #define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m)))
  381. #define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004))
  382. #define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008))
  383. #define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C))
  384. #define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014))
  385. #define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
  386. #define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
  387. #define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
  388. void init_memory_bridge(void)
  389. {
  390. u32 reg;
  391. /*
  392. * M_HS_CORE has one unic register - BOOT.
  393. * We need to clean boot mirror (BOOT[1:0]) bits in them.
  394. */
  395. reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
  396. writel(reg, CREG_AXI_M_HS_CORE_BOOT);
  397. writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
  398. writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
  399. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
  400. writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
  401. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
  402. writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
  403. writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
  404. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
  405. writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
  406. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
  407. writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
  408. writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
  409. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
  410. writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
  411. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
  412. writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
  413. writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
  414. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
  415. writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
  416. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
  417. writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
  418. writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
  419. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
  420. writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
  421. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
  422. writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
  423. writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
  424. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
  425. writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
  426. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
  427. writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
  428. writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
  429. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
  430. writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
  431. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
  432. writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
  433. writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
  434. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
  435. writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
  436. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
  437. writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
  438. writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
  439. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
  440. writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
  441. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
  442. writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
  443. writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
  444. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
  445. writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
  446. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
  447. writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
  448. writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
  449. writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
  450. writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
  451. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
  452. writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
  453. writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
  454. writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
  455. writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
  456. writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
  457. writel(0x00000000, CREG_PAE);
  458. writel(UPDATE_VAL, CREG_PAE_UPDT);
  459. }
  460. static void setup_clocks(void)
  461. {
  462. ulong rate;
  463. /* Setup CPU clock */
  464. if (env_common.cpu_freq.set) {
  465. rate = env_common.cpu_freq.val;
  466. soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
  467. }
  468. /* Setup TUN clock */
  469. if (env_common.tun_freq.set) {
  470. rate = env_common.tun_freq.val;
  471. if (rate)
  472. soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
  473. else
  474. soc_clk_ctl("tun-clk", NULL, CLK_OFF);
  475. }
  476. if (env_common.axi_freq.set) {
  477. rate = env_common.axi_freq.val;
  478. soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ);
  479. }
  480. }
  481. static void do_init_cluster(void)
  482. {
  483. /*
  484. * A multi-core ARC HS configuration always includes only one
  485. * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the
  486. * cores.
  487. */
  488. init_cluster_nvlim();
  489. }
  490. static int check_master_cpu_id(void)
  491. {
  492. if (CPU_ID_GET() == MASTER_CPU_ID)
  493. return 0;
  494. pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET());
  495. return -ENOENT;
  496. }
  497. static noinline int prepare_cpus(void)
  498. {
  499. int ret;
  500. ret = check_master_cpu_id();
  501. if (ret)
  502. return ret;
  503. ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used);
  504. if (ret)
  505. return ret;
  506. printf("CPU start mask is %#x\n", env_common.core_mask.val);
  507. do_init_slave_cpus();
  508. do_init_master_cpu();
  509. do_init_cluster();
  510. return 0;
  511. }
  512. static int hsdk_go_run(u32 cpu_start_reg)
  513. {
  514. /* Cleanup caches, disable interrupts */
  515. cleanup_before_go();
  516. if (env_common.halt_on_boot)
  517. halt_this_cpu();
  518. /*
  519. * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
  520. * cores but we leave them for gebug purposes.
  521. */
  522. __builtin_arc_nop();
  523. __builtin_arc_nop();
  524. __builtin_arc_nop();
  525. /* Kick chosen slave CPUs */
  526. writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
  527. if (is_cpu_used(MASTER_CPU_ID))
  528. ((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))();
  529. else
  530. halt_this_cpu();
  531. pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET());
  532. /*
  533. * We will never return after executing our program if master cpu used
  534. * otherwise halt master cpu manually.
  535. */
  536. while (true)
  537. halt_this_cpu();
  538. return 0;
  539. }
  540. int board_prep_linux(bootm_headers_t *images)
  541. {
  542. int ret, ofst;
  543. char mask[15];
  544. ret = envs_read_validate_common(env_map_mask);
  545. if (ret)
  546. return ret;
  547. /* Rollback to default values */
  548. if (!env_common.core_mask.set) {
  549. env_common.core_mask.val = ALL_CPU_MASK;
  550. env_common.core_mask.set = true;
  551. }
  552. printf("CPU start mask is %#x\n", env_common.core_mask.val);
  553. if (!is_cpu_used(MASTER_CPU_ID))
  554. pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n");
  555. /*
  556. * If we want to launch linux on all CPUs we don't need to patch
  557. * linux DTB as it is default configuration
  558. */
  559. if (env_common.core_mask.val == ALL_CPU_MASK)
  560. return 0;
  561. if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
  562. pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
  563. return 0;
  564. }
  565. /* patch '/possible-cpus' property according to cpu mask */
  566. ofst = fdt_path_offset(images->ft_addr, "/");
  567. sprintf(mask, "%s%s%s%s",
  568. is_cpu_used(0) ? "0," : "",
  569. is_cpu_used(1) ? "1," : "",
  570. is_cpu_used(2) ? "2," : "",
  571. is_cpu_used(3) ? "3," : "");
  572. ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask);
  573. /*
  574. * If we failed to patch '/possible-cpus' property we don't need break
  575. * linux loading process: kernel will handle it but linux will print
  576. * warning like "Timeout: CPU1 FAILED to comeup !!!".
  577. * So warn here about error, but return 0 like no error had occurred.
  578. */
  579. if (ret)
  580. pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n",
  581. ret);
  582. return 0;
  583. }
  584. void board_jump_and_run(ulong entry, int zero, int arch, uint params)
  585. {
  586. void (*kernel_entry)(int zero, int arch, uint params);
  587. u32 cpu_start_reg;
  588. kernel_entry = (void (*)(int, int, uint))entry;
  589. /* Prepare CREG_CPU_START for kicking chosen CPUs */
  590. cpu_start_reg = prepare_cpu_ctart_reg();
  591. /* In case of run without hsdk_init */
  592. slave_cpu_set_boot_addr(entry);
  593. /* In case of run with hsdk_init */
  594. for (u32 i = 0; i < NR_CPUS; i++) {
  595. env_core.entry[i].val = entry;
  596. env_core.entry[i].set = true;
  597. }
  598. /* sync cross_cpu struct as we updated core-entry variables */
  599. sync_cross_cpu_data();
  600. /* Kick chosen slave CPUs */
  601. writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
  602. if (is_cpu_used(0))
  603. kernel_entry(zero, arch, params);
  604. }
  605. static int hsdk_go_prepare_and_run(void)
  606. {
  607. /* Prepare CREG_CPU_START for kicking chosen CPUs */
  608. u32 reg = prepare_cpu_ctart_reg();
  609. if (env_common.halt_on_boot)
  610. printf("CPU will halt before application start, start application with debugger.\n");
  611. return hsdk_go_run(reg);
  612. }
  613. static int do_hsdk_go(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  614. {
  615. int ret;
  616. /*
  617. * Check for 'halt' parameter. 'halt' = enter halt-mode just before
  618. * starting the application; can be used for debug.
  619. */
  620. if (argc > 1) {
  621. env_common.halt_on_boot = !strcmp(argv[1], "halt");
  622. if (!env_common.halt_on_boot) {
  623. pr_err("Unrecognised parameter: \'%s\'\n", argv[1]);
  624. return CMD_RET_FAILURE;
  625. }
  626. }
  627. ret = check_master_cpu_id();
  628. if (ret)
  629. return ret;
  630. ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used);
  631. if (ret)
  632. return ret;
  633. /* sync cross_cpu struct as we updated core-entry variables */
  634. sync_cross_cpu_data();
  635. ret = hsdk_go_prepare_and_run();
  636. return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
  637. }
  638. U_BOOT_CMD(
  639. hsdk_go, 3, 0, do_hsdk_go,
  640. "Synopsys HSDK specific command",
  641. " - Boot stand-alone application on HSDK\n"
  642. "hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
  643. );
  644. static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  645. {
  646. static bool done = false;
  647. int ret;
  648. /* hsdk_init can be run only once */
  649. if (done) {
  650. printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
  651. return CMD_RET_FAILURE;
  652. }
  653. ret = prepare_cpus();
  654. if (!ret)
  655. done = true;
  656. return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
  657. }
  658. U_BOOT_CMD(
  659. hsdk_init, 1, 0, do_hsdk_init,
  660. "Synopsys HSDK specific command",
  661. "- Init HSDK HW\n"
  662. );
  663. static int do_hsdk_clock_set(cmd_tbl_t *cmdtp, int flag, int argc,
  664. char *const argv[])
  665. {
  666. int ret = 0;
  667. /* Strip off leading subcommand argument */
  668. argc--;
  669. argv++;
  670. envs_cleanup_common(env_map_clock);
  671. if (!argc) {
  672. printf("Set clocks to values specified in environment\n");
  673. ret = envs_read_common(env_map_clock);
  674. } else {
  675. printf("Set clocks to values specified in args\n");
  676. ret = args_envs_enumerate(env_map_clock, 2, argc, argv);
  677. }
  678. if (ret)
  679. return CMD_RET_FAILURE;
  680. ret = envs_validate_common(env_map_clock);
  681. if (ret)
  682. return CMD_RET_FAILURE;
  683. /* Setup clock tree HW */
  684. setup_clocks();
  685. return CMD_RET_SUCCESS;
  686. }
  687. static int do_hsdk_clock_get(cmd_tbl_t *cmdtp, int flag, int argc,
  688. char *const argv[])
  689. {
  690. ulong rate;
  691. if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ))
  692. return CMD_RET_FAILURE;
  693. if (env_set_ulong("cpu_freq", rate))
  694. return CMD_RET_FAILURE;
  695. if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ))
  696. return CMD_RET_FAILURE;
  697. if (env_set_ulong("tun_freq", rate))
  698. return CMD_RET_FAILURE;
  699. if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ))
  700. return CMD_RET_FAILURE;
  701. if (env_set_ulong("axi_freq", rate))
  702. return CMD_RET_FAILURE;
  703. printf("Clock values are saved to environment\n");
  704. return CMD_RET_SUCCESS;
  705. }
  706. static int do_hsdk_clock_print(cmd_tbl_t *cmdtp, int flag, int argc,
  707. char *const argv[])
  708. {
  709. /* Main clocks */
  710. soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
  711. soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
  712. soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
  713. soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
  714. return CMD_RET_SUCCESS;
  715. }
  716. static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int flag, int argc,
  717. char *const argv[])
  718. {
  719. /*
  720. * NOTE: as of today we don't use some peripherals like HDMI / EBI
  721. * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll",
  722. * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully
  723. * functional and we can print their clocks if it is required
  724. */
  725. /* CPU clock domain */
  726. soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ);
  727. soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
  728. printf("\n");
  729. /* SYS clock domain */
  730. soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ);
  731. soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ);
  732. soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
  733. soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
  734. soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
  735. soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
  736. /* soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ); */
  737. soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
  738. soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
  739. soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
  740. soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
  741. soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
  742. soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
  743. soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ);
  744. soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ);
  745. /* soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */
  746. soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ);
  747. printf("\n");
  748. /* DDR clock domain */
  749. soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
  750. printf("\n");
  751. /* HDMI clock domain */
  752. /* soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ); */
  753. /* soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ); */
  754. /* printf("\n"); */
  755. /* TUN clock domain */
  756. soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
  757. soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
  758. soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
  759. soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
  760. printf("\n");
  761. return CMD_RET_SUCCESS;
  762. }
  763. cmd_tbl_t cmd_hsdk_clock[] = {
  764. U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""),
  765. U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""),
  766. U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""),
  767. U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""),
  768. };
  769. static int do_hsdk_clock(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  770. {
  771. cmd_tbl_t *c;
  772. if (argc < 2)
  773. return CMD_RET_USAGE;
  774. /* Strip off leading 'hsdk_clock' command argument */
  775. argc--;
  776. argv++;
  777. c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock));
  778. if (!c)
  779. return CMD_RET_USAGE;
  780. return c->cmd(cmdtp, flag, argc, argv);
  781. }
  782. U_BOOT_CMD(
  783. hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock,
  784. "Synopsys HSDK specific clock command",
  785. "set - Set clock to values specified in environment / command line arguments\n"
  786. "hsdk_clock get - Save clock values to environment\n"
  787. "hsdk_clock print - Print main clock values to console\n"
  788. "hsdk_clock print_all - Print all clock values to console\n"
  789. );
  790. /* init calls */
  791. int board_early_init_f(void)
  792. {
  793. /*
  794. * Setup AXI apertures unconditionally as we want to have DDR
  795. * in 0x00000000 region when we are kicking slave cpus.
  796. */
  797. init_memory_bridge();
  798. /*
  799. * Switch SDIO external ciu clock divider from default div-by-8 to
  800. * minimum possible div-by-2.
  801. */
  802. writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
  803. return 0;
  804. }
  805. int board_early_init_r(void)
  806. {
  807. /*
  808. * TODO: Init USB here to be able read environment from USB MSD.
  809. * It can be done with usb_init() call. We can't do it right now
  810. * due to brocken USB IP SW reset and lack of USB IP HW reset in
  811. * linux kernel (if we init USB here we will break USB in linux)
  812. */
  813. /*
  814. * Flush all d$ as we want to use uncached area with st.di / ld.di
  815. * instructions and we don't want to have any dirty line in L1d$ or SL$
  816. * in this area. It is enough to flush all d$ once here as we access to
  817. * uncached area with regular st (non .di) instruction only when we copy
  818. * data during u-boot relocation.
  819. */
  820. flush_dcache_all();
  821. printf("Relocation Offset is: %08lx\n", gd->reloc_off);
  822. return 0;
  823. }
  824. int board_late_init(void)
  825. {
  826. /*
  827. * Populate environment with clock frequency values -
  828. * run hsdk_clock get callback without uboot command run.
  829. */
  830. do_hsdk_clock_get(NULL, 0, 0, NULL);
  831. return 0;
  832. }
  833. int checkboard(void)
  834. {
  835. puts("Board: Synopsys ARC HS Development Kit\n");
  836. return 0;
  837. };