axs10x.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <dwmmc.h>
  8. #include <malloc.h>
  9. #include <asm/arcregs.h>
  10. #include "axs10x.h"
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #define AXS_MB_CREG 0xE0011000
  13. int board_early_init_f(void)
  14. {
  15. if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
  16. gd->board_type = AXS_MB_V3;
  17. else
  18. gd->board_type = AXS_MB_V2;
  19. return 0;
  20. }
  21. #ifdef CONFIG_ISA_ARCV2
  22. void board_jump_and_run(ulong entry, int zero, int arch, uint params)
  23. {
  24. void (*kernel_entry)(int zero, int arch, uint params);
  25. kernel_entry = (void (*)(int, int, uint))entry;
  26. smp_set_core_boot_addr(entry, -1);
  27. smp_kick_all_cpus();
  28. kernel_entry(zero, arch, params);
  29. }
  30. #define RESET_VECTOR_ADDR 0x0
  31. void smp_set_core_boot_addr(unsigned long addr, int corenr)
  32. {
  33. /* All cores have reset vector pointing to 0 */
  34. writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
  35. /* Make sure other cores see written value in memory */
  36. flush_dcache_all();
  37. }
  38. void smp_kick_all_cpus(void)
  39. {
  40. /* CPU start CREG */
  41. #define AXC003_CREG_CPU_START 0xF0001400
  42. /* Bits positions in CPU start CREG */
  43. #define BITS_START 0
  44. #define BITS_START_MODE 4
  45. #define BITS_CORE_SEL 9
  46. /*
  47. * In axs103 v1.1 START bits semantics has changed quite a bit.
  48. * We used to have a generic START bit for all cores selected by CORE_SEL mask.
  49. * But now we don't touch CORE_SEL at all because we have a dedicated START bit
  50. * for each core:
  51. * bit 0: Core 0 (master)
  52. * bit 1: Core 1 (slave)
  53. */
  54. #define BITS_START_CORE1 1
  55. #define ARCVER_HS38_3_0 0x53
  56. int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
  57. int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
  58. if (core_family < ARCVER_HS38_3_0) {
  59. cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
  60. cmd &= ~(1 << BITS_START_MODE);
  61. } else {
  62. cmd |= (1 << BITS_START_CORE1);
  63. }
  64. writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
  65. }
  66. #endif
  67. int checkboard(void)
  68. {
  69. printf("Board: ARC Software Development Platform AXS%s\n",
  70. is_isa_arcv2() ? "103" : "101");
  71. return 0;
  72. };