fpga.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <spartan3.h>
  7. #include <command.h>
  8. #include <asm/gpio.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/spr_misc.h>
  12. #include <asm/arch/spr_ssp.h>
  13. /*
  14. * FPGA program pin configuration on X600:
  15. *
  16. * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
  17. * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
  18. * 16bit serial writes via this SSP port to write the data bits into the
  19. * FPGA.
  20. */
  21. #define CONFIG_SYS_FPGA_PROG 2
  22. #define CONFIG_SYS_FPGA_DONE 3
  23. /*
  24. * Set the active-low FPGA reset signal.
  25. */
  26. static void fpga_reset(int assert)
  27. {
  28. /*
  29. * On x600 we have no means to toggle the FPGA reset signal
  30. */
  31. debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
  32. }
  33. /*
  34. * Set the FPGA's active-low SelectMap program line to the specified level
  35. */
  36. static int fpga_pgm_fn(int assert, int flush, int cookie)
  37. {
  38. debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
  39. gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
  40. return assert;
  41. }
  42. /*
  43. * Test the state of the active-low FPGA INIT line. Return 1 on INIT
  44. * asserted (low).
  45. */
  46. static int fpga_init_fn(int cookie)
  47. {
  48. static int state;
  49. debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
  50. /*
  51. * On x600, the FPGA INIT signal is not connected to the SoC.
  52. * We can't read the INIT status. Let's return the "correct"
  53. * INIT signal state generated via a local state-machine.
  54. */
  55. if (++state == 1) {
  56. return 1;
  57. } else {
  58. state = 0;
  59. return 0;
  60. }
  61. }
  62. /*
  63. * Test the state of the active-high FPGA DONE pin
  64. */
  65. static int fpga_done_fn(int cookie)
  66. {
  67. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  68. /*
  69. * Wait for Tx-FIFO to become empty before looking for DONE
  70. */
  71. while (!(readl(&ssp->sspsr) & SSPSR_TFE))
  72. ;
  73. if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
  74. return 1;
  75. else
  76. return 0;
  77. }
  78. /*
  79. * FPGA pre-configuration function. Just make sure that
  80. * FPGA reset is asserted to keep the FPGA from starting up after
  81. * configuration.
  82. */
  83. static int fpga_pre_config_fn(int cookie)
  84. {
  85. debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
  86. fpga_reset(true);
  87. return 0;
  88. }
  89. /*
  90. * FPGA post configuration function. Blip the FPGA reset line and then see if
  91. * the FPGA appears to be running.
  92. */
  93. static int fpga_post_config_fn(int cookie)
  94. {
  95. int rc = 0;
  96. debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
  97. fpga_reset(true);
  98. udelay(100);
  99. fpga_reset(false);
  100. udelay(100);
  101. return rc;
  102. }
  103. static int fpga_clk_fn(int assert_clk, int flush, int cookie)
  104. {
  105. /*
  106. * No dedicated clock signal on x600 (data & clock generated)
  107. * in SSP interface. So we don't have to do anything here.
  108. */
  109. return assert_clk;
  110. }
  111. static int fpga_wr_fn(int assert_write, int flush, int cookie)
  112. {
  113. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  114. static int count;
  115. static u16 data;
  116. /*
  117. * First collect 16 bits of data
  118. */
  119. data = data << 1;
  120. if (assert_write)
  121. data |= 1;
  122. /*
  123. * If 16 bits are not available, return for more bits
  124. */
  125. count++;
  126. if (count != 16)
  127. return assert_write;
  128. count = 0;
  129. /*
  130. * Wait for Tx-FIFO to become ready
  131. */
  132. while (!(readl(&ssp->sspsr) & SSPSR_TNF))
  133. ;
  134. /* Send 16 bits to FPGA via SSP bus */
  135. writel(data, &ssp->sspdr);
  136. return assert_write;
  137. }
  138. static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
  139. fpga_pre_config_fn,
  140. fpga_pgm_fn,
  141. fpga_clk_fn,
  142. fpga_init_fn,
  143. fpga_done_fn,
  144. fpga_wr_fn,
  145. fpga_post_config_fn,
  146. };
  147. static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
  148. XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
  149. };
  150. /*
  151. * Initialize the SelectMap interface. We assume that the mode and the
  152. * initial state of all of the port pins have already been set!
  153. */
  154. static void fpga_serialslave_init(void)
  155. {
  156. debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
  157. fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
  158. }
  159. static int expi_setup(int freq)
  160. {
  161. struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  162. int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
  163. pll2_m = (freq * 2) / 1000;
  164. pll2_n = 15;
  165. pll2_p = 1;
  166. expi_x = 1;
  167. expi_y = 2;
  168. /*
  169. * Disable reset, Low compression, Disable retiming, Enable Expi,
  170. * Enable soft reset, DMA, PLL2, Internal
  171. */
  172. writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
  173. EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
  174. EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
  175. &misc->expi_clk_cfg);
  176. /*
  177. * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
  178. * Enable PLL2, Disable reset
  179. */
  180. writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
  181. writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
  182. PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
  183. /*
  184. * Disable soft reset
  185. */
  186. clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
  187. return 0;
  188. }
  189. /*
  190. * Initialize the fpga
  191. */
  192. int x600_init_fpga(void)
  193. {
  194. struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
  195. struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  196. /* Enable SSP2 clock */
  197. writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
  198. &misc->periph1_clken);
  199. /* Set EXPI clock to 45 MHz */
  200. expi_setup(45000);
  201. /* Configure GPIO directions */
  202. gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
  203. gpio_direction_input(CONFIG_SYS_FPGA_DONE);
  204. writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
  205. writel(SSPCR1_SSE, &ssp->sspcr1);
  206. /*
  207. * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
  208. * speed.
  209. *
  210. * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
  211. * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
  212. */
  213. writel(2, &ssp->sspcpsr);
  214. fpga_init();
  215. fpga_serialslave_init();
  216. debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
  217. fpga_add(fpga_xilinx, &fpga[0]);
  218. return 0;
  219. }