clearfog.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <miiphy.h>
  8. #include <netdev.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/soc.h>
  12. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  13. #include <../serdes/a38x/high_speed_env_spec.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. /*
  16. * Those values and defines are taken from the Marvell U-Boot version
  17. * "u-boot-2013.01-15t1-clearfog"
  18. */
  19. #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
  20. #define BOARD_GPP_OUT_ENA_MID 0xffffffff
  21. #define BOARD_GPP_OUT_VAL_LOW 0x0
  22. #define BOARD_GPP_OUT_VAL_MID 0x0
  23. #define BOARD_GPP_POL_LOW 0x0
  24. #define BOARD_GPP_POL_MID 0x0
  25. static struct serdes_map board_serdes_map[] = {
  26. {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  27. {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  28. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  29. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  30. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  31. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  32. };
  33. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  34. {
  35. *serdes_map_array = board_serdes_map;
  36. *count = ARRAY_SIZE(board_serdes_map);
  37. return 0;
  38. }
  39. /*
  40. * Define the DDR layout / topology here in the board file. This will
  41. * be used by the DDR3 init code in the SPL U-Boot version to configure
  42. * the DDR3 controller.
  43. */
  44. static struct mv_ddr_topology_map board_topology_map = {
  45. DEBUG_LEVEL_ERROR,
  46. 0x1, /* active interfaces */
  47. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  48. { { { {0x1, 0, 0, 0},
  49. {0x1, 0, 0, 0},
  50. {0x1, 0, 0, 0},
  51. {0x1, 0, 0, 0},
  52. {0x1, 0, 0, 0} },
  53. SPEED_BIN_DDR_1600K, /* speed_bin */
  54. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  55. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  56. MV_DDR_FREQ_800, /* frequency */
  57. 0, 0, /* cas_wl cas_l */
  58. MV_DDR_TEMP_LOW, /* temperature */
  59. MV_DDR_TIM_DEFAULT} }, /* timing */
  60. BUS_MASK_32BIT, /* Busses mask */
  61. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  62. { {0} }, /* raw spd data */
  63. {0} /* timing parameters */
  64. };
  65. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  66. {
  67. /* Return the board topology as defined in the board code */
  68. return &board_topology_map;
  69. }
  70. int board_early_init_f(void)
  71. {
  72. /* Configure MPP */
  73. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  74. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  75. writel(0x10400011, MVEBU_MPP_BASE + 0x08);
  76. writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
  77. writel(0x44400002, MVEBU_MPP_BASE + 0x10);
  78. writel(0x41144004, MVEBU_MPP_BASE + 0x14);
  79. writel(0x40333333, MVEBU_MPP_BASE + 0x18);
  80. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  81. /* Set GPP Out value */
  82. writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  83. writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  84. /* Set GPP Polarity */
  85. writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  86. writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  87. /* Set GPP Out Enable */
  88. writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  89. writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  90. return 0;
  91. }
  92. int board_init(void)
  93. {
  94. /* Address of boot parameters */
  95. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  96. /* Toggle GPIO41 to reset onboard switch and phy */
  97. clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
  98. clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
  99. /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
  100. clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
  101. clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
  102. mdelay(1);
  103. setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
  104. setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
  105. mdelay(10);
  106. return 0;
  107. }
  108. int checkboard(void)
  109. {
  110. puts("Board: SolidRun ClearFog\n");
  111. return 0;
  112. }
  113. int board_eth_init(bd_t *bis)
  114. {
  115. cpu_eth_init(bis); /* Built in controller(s) come first */
  116. return pci_eth_init(bis);
  117. }