board.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for TI AM335X based draco board
  4. * (C) Copyright 2013 Siemens Schweiz AG
  5. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * Based on:
  8. *
  9. * Board functions for TI AM335X based boards
  10. * u-boot:/board/ti/am335x/board.c
  11. *
  12. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13. */
  14. #include <common.h>
  15. #include <env.h>
  16. #include <errno.h>
  17. #include <init.h>
  18. #include <spl.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/omap.h>
  22. #include <asm/arch/ddr_defs.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/gpio.h>
  25. #include <asm/arch/mmc_host_def.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/arch/mem.h>
  28. #include <asm/io.h>
  29. #include <asm/emif.h>
  30. #include <asm/gpio.h>
  31. #include <i2c.h>
  32. #include <miiphy.h>
  33. #include <cpsw.h>
  34. #include <watchdog.h>
  35. #include "board.h"
  36. #include "../common/factoryset.h"
  37. #include <nand.h>
  38. #ifdef CONFIG_SPL_BUILD
  39. static struct draco_baseboard_id __attribute__((section(".data"))) settings;
  40. #if DDR_PLL_FREQ == 303
  41. #if !defined(CONFIG_TARGET_ETAMIN)
  42. /* Default@303MHz-i0 */
  43. const struct ddr3_data ddr3_default = {
  44. 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
  45. 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
  46. 0x0000093B, 0x0000014A,
  47. "default name @303MHz \0",
  48. "default marking \0",
  49. };
  50. #else
  51. /* etamin board */
  52. const struct ddr3_data ddr3_default = {
  53. 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
  54. 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
  55. 0x0000093B, 0x0000018A,
  56. "test-etamin \0",
  57. "generic-8Gbit \0",
  58. };
  59. #endif
  60. #elif DDR_PLL_FREQ == 400
  61. /* Default@400MHz-i0 */
  62. const struct ddr3_data ddr3_default = {
  63. 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
  64. 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
  65. 0x00000618, 0x0000014A,
  66. "default name @400MHz \0",
  67. "default marking \0",
  68. };
  69. #endif
  70. static void set_default_ddr3_timings(void)
  71. {
  72. printf("Set default DDR3 settings\n");
  73. settings.ddr3 = ddr3_default;
  74. }
  75. static void print_ddr3_timings(void)
  76. {
  77. printf("\nDDR3\n");
  78. printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
  79. printf("device:\t\t%s\n", settings.ddr3.manu_name);
  80. printf("marking:\t%s\n", settings.ddr3.manu_marking);
  81. printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
  82. "default", "diff");
  83. PRINTARGS(magic);
  84. PRINTARGS(version);
  85. PRINTARGS(ddr3_sratio);
  86. PRINTARGS(iclkout);
  87. PRINTARGS(dt0rdsratio0);
  88. PRINTARGS(dt0wdsratio0);
  89. PRINTARGS(dt0fwsratio0);
  90. PRINTARGS(dt0wrsratio0);
  91. PRINTARGS(sdram_tim1);
  92. PRINTARGS(sdram_tim2);
  93. PRINTARGS(sdram_tim3);
  94. PRINTARGS(emif_ddr_phy_ctlr_1);
  95. PRINTARGS(sdram_config);
  96. PRINTARGS(ref_ctrl);
  97. PRINTARGS(ioctr_val);
  98. }
  99. static void print_chip_data(void)
  100. {
  101. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  102. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  103. printf("\nCPU BOARD\n");
  104. printf("device: \t'%s'\n", settings.chip.sdevname);
  105. printf("hw version: \t'%s'\n", settings.chip.shwver);
  106. printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
  107. }
  108. #endif /* CONFIG_SPL_BUILD */
  109. #define AM335X_NAND_ECC_MASK 0x0f
  110. #define AM335X_NAND_ECC_TYPE_16 0x02
  111. static int ecc_type;
  112. struct am335x_nand_geometry {
  113. u32 magic;
  114. u8 nand_geo_addr;
  115. u8 nand_geo_page;
  116. u8 nand_bus;
  117. };
  118. static int draco_read_nand_geometry(void)
  119. {
  120. struct am335x_nand_geometry geo;
  121. /* Read NAND geometry */
  122. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
  123. (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
  124. printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
  125. return -EIO;
  126. }
  127. if (geo.magic != 0xa657b310) {
  128. printf("%s: bad magic: %x\n", __func__, geo.magic);
  129. return -EFAULT;
  130. }
  131. if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
  132. ecc_type = 16;
  133. else
  134. ecc_type = 8;
  135. return 0;
  136. }
  137. /*
  138. * Read header information from EEPROM into global structure.
  139. */
  140. static int read_eeprom(void)
  141. {
  142. /* Check if baseboard eeprom is available */
  143. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  144. printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  145. return 1;
  146. }
  147. #ifdef CONFIG_SPL_BUILD
  148. /* Read Siemens eeprom data (DDR3) */
  149. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
  150. (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
  151. printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
  152. set_default_ddr3_timings();
  153. }
  154. /* Read Siemens eeprom data (CHIP) */
  155. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
  156. (uchar *)&settings.chip, sizeof(settings.chip)))
  157. printf("Could not read chip settings\n");
  158. if (ddr3_default.magic == settings.ddr3.magic &&
  159. ddr3_default.version == settings.ddr3.version) {
  160. printf("Using DDR3 settings from EEPROM\n");
  161. } else {
  162. if (ddr3_default.magic != settings.ddr3.magic)
  163. printf("Warning: No valid DDR3 data in eeprom.\n");
  164. if (ddr3_default.version != settings.ddr3.version)
  165. printf("Warning: DDR3 data version does not match.\n");
  166. printf("Using default settings\n");
  167. set_default_ddr3_timings();
  168. }
  169. if (MAGIC_CHIP == settings.chip.magic)
  170. print_chip_data();
  171. else
  172. printf("Warning: No chip data in eeprom\n");
  173. print_ddr3_timings();
  174. return draco_read_nand_geometry();
  175. #endif
  176. return 0;
  177. }
  178. #ifdef CONFIG_SPL_BUILD
  179. static void board_init_ddr(void)
  180. {
  181. struct emif_regs draco_ddr3_emif_reg_data = {
  182. .zq_config = 0x50074BE4,
  183. };
  184. struct ddr_data draco_ddr3_data = {
  185. };
  186. struct cmd_control draco_ddr3_cmd_ctrl_data = {
  187. };
  188. struct ctrl_ioregs draco_ddr3_ioregs = {
  189. };
  190. /* pass values from eeprom */
  191. draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
  192. draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
  193. draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
  194. draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
  195. settings.ddr3.emif_ddr_phy_ctlr_1;
  196. draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
  197. draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
  198. draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
  199. draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
  200. draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
  201. draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
  202. draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
  203. draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
  204. draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
  205. draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
  206. draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
  207. draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
  208. draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
  209. draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
  210. draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
  211. draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
  212. draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
  213. draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
  214. config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
  215. &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
  216. }
  217. static void spl_siemens_board_init(void)
  218. {
  219. return;
  220. }
  221. #endif /* if def CONFIG_SPL_BUILD */
  222. #ifdef CONFIG_BOARD_LATE_INIT
  223. int board_late_init(void)
  224. {
  225. int ret;
  226. ret = draco_read_nand_geometry();
  227. if (ret != 0)
  228. return ret;
  229. nand_curr_device = 0;
  230. omap_nand_switch_ecc(1, ecc_type);
  231. #ifdef CONFIG_TARGET_ETAMIN
  232. nand_curr_device = 1;
  233. omap_nand_switch_ecc(1, ecc_type);
  234. #endif
  235. #ifdef CONFIG_FACTORYSET
  236. /* Set ASN in environment*/
  237. if (factory_dat.asn[0] != 0) {
  238. env_set("dtb_name", (char *)factory_dat.asn);
  239. } else {
  240. /* dtb suffix gets added in load script */
  241. env_set("dtb_name", "am335x-draco");
  242. }
  243. #else
  244. env_set("dtb_name", "am335x-draco");
  245. #endif
  246. return 0;
  247. }
  248. #endif
  249. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  250. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  251. static void cpsw_control(int enabled)
  252. {
  253. /* VTP can be added here */
  254. return;
  255. }
  256. static struct cpsw_slave_data cpsw_slaves[] = {
  257. {
  258. .slave_reg_ofs = 0x208,
  259. .sliver_reg_ofs = 0xd80,
  260. .phy_addr = 0,
  261. .phy_if = PHY_INTERFACE_MODE_MII,
  262. },
  263. };
  264. static struct cpsw_platform_data cpsw_data = {
  265. .mdio_base = CPSW_MDIO_BASE,
  266. .cpsw_base = CPSW_BASE,
  267. .mdio_div = 0xff,
  268. .channels = 4,
  269. .cpdma_reg_ofs = 0x800,
  270. .slaves = 1,
  271. .slave_data = cpsw_slaves,
  272. .ale_reg_ofs = 0xd00,
  273. .ale_entries = 1024,
  274. .host_port_reg_ofs = 0x108,
  275. .hw_stats_reg_ofs = 0x900,
  276. .bd_ram_ofs = 0x2000,
  277. .mac_control = (1 << 5),
  278. .control = cpsw_control,
  279. .host_port_num = 0,
  280. .version = CPSW_CTRL_VERSION_2,
  281. };
  282. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  283. (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
  284. int board_eth_init(bd_t *bis)
  285. {
  286. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  287. int n = 0;
  288. int rv;
  289. factoryset_env_set();
  290. /* Set rgmii mode and enable rmii clock to be sourced from chip */
  291. writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
  292. rv = cpsw_register(&cpsw_data);
  293. if (rv < 0)
  294. printf("Error %d registering CPSW switch\n", rv);
  295. else
  296. n += rv;
  297. return n;
  298. }
  299. static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
  300. char *const argv[])
  301. {
  302. /* Reset SMSC LAN9303 switch for default configuration */
  303. gpio_request(GPIO_LAN9303_NRST, "nRST");
  304. gpio_direction_output(GPIO_LAN9303_NRST, 0);
  305. /* assert active low reset for 200us */
  306. udelay(200);
  307. gpio_set_value(GPIO_LAN9303_NRST, 1);
  308. return 0;
  309. };
  310. U_BOOT_CMD(
  311. switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
  312. "Reset LAN9303 switch via its reset pin",
  313. ""
  314. );
  315. #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
  316. #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
  317. #ifdef CONFIG_NAND_CS_INIT
  318. /* GPMC definitions for second nand cs1 */
  319. static const u32 gpmc_nand_config[] = {
  320. ETAMIN_NAND_GPMC_CONFIG1,
  321. ETAMIN_NAND_GPMC_CONFIG2,
  322. ETAMIN_NAND_GPMC_CONFIG3,
  323. ETAMIN_NAND_GPMC_CONFIG4,
  324. ETAMIN_NAND_GPMC_CONFIG5,
  325. ETAMIN_NAND_GPMC_CONFIG6,
  326. /*CONFIG7- computed as params */
  327. };
  328. static void board_nand_cs_init(void)
  329. {
  330. enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
  331. 0x18000000, GPMC_SIZE_16M);
  332. }
  333. #endif
  334. #include "../common/board.c"