tlb.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <asm/mmu.h>
  10. struct fsl_e_tlb_entry tlb_table[] = {
  11. /* TLB 0 - for temp stack in cache */
  12. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  13. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  14. 0, 0, BOOKE_PAGESZ_4K, 0),
  15. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16. CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  17. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  18. 0, 0, BOOKE_PAGESZ_4K, 0),
  19. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  20. CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22. 0, 0, BOOKE_PAGESZ_4K, 0),
  23. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24. CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26. 0, 0, BOOKE_PAGESZ_4K, 0),
  27. /*
  28. * TLB 0: 64M Non-cacheable, guarded
  29. * 0xfc000000 56M unused
  30. * 0xff800000 8M boot FLASH
  31. * .... or ....
  32. * 0xfc000000 64M user flash
  33. *
  34. * Out of reset this entry is only 4K.
  35. */
  36. SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
  37. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38. 0, 0, BOOKE_PAGESZ_64M, 1),
  39. /*
  40. * TLB 1: 1G Non-cacheable, guarded
  41. * 0x80000000 512M PCI1 MEM
  42. * 0xa0000000 512M PCIe MEM
  43. */
  44. SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
  45. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  46. 0, 1, BOOKE_PAGESZ_1G, 1),
  47. /*
  48. * TLB 2: 64M Non-cacheable, guarded
  49. * 0xe0000000 1M CCSRBAR
  50. * 0xe2000000 8M PCI1 IO
  51. * 0xe2800000 8M PCIe IO
  52. */
  53. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  54. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  55. 0, 2, BOOKE_PAGESZ_64M, 1),
  56. #ifdef CONFIG_SYS_LBC_SDRAM_BASE
  57. /*
  58. * TLB 3: 64M Cacheable, non-guarded
  59. * 0xf0000000 64M LBC SDRAM First half
  60. */
  61. SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
  62. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  63. 0, 3, BOOKE_PAGESZ_64M, 1),
  64. /*
  65. * TLB 4: 64M Cacheable, non-guarded
  66. * 0xf4000000 64M LBC SDRAM Second half
  67. */
  68. SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
  69. CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
  70. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  71. 0, 4, BOOKE_PAGESZ_64M, 1),
  72. #endif
  73. /*
  74. * TLB 5: 16M Cacheable, non-guarded
  75. * 0xf8000000 1M 7-segment LED display
  76. * 0xf8100000 1M User switches
  77. * 0xf8300000 1M Board revision
  78. * 0xf8b00000 1M EEPROM
  79. */
  80. SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
  81. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82. 0, 5, BOOKE_PAGESZ_16M, 1),
  83. #ifndef CONFIG_SYS_ALT_BOOT
  84. /*
  85. * TLB 6: 64M Non-cacheable, guarded
  86. * 0xec000000 64M 64MB user FLASH
  87. */
  88. SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
  89. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  90. 0, 6, BOOKE_PAGESZ_64M, 1),
  91. #else
  92. /*
  93. * TLB 6: 4M Non-cacheable, guarded
  94. * 0xef800000 4M 1st 1/2 8MB soldered FLASH
  95. */
  96. SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
  97. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  98. 0, 6, BOOKE_PAGESZ_4M, 1),
  99. /*
  100. * TLB 7: 4M Non-cacheable, guarded
  101. * 0xefc00000 4M 2nd half 8MB soldered FLASH
  102. */
  103. SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
  104. CONFIG_SYS_ALT_FLASH + 0x400000,
  105. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  106. 0, 7, BOOKE_PAGESZ_4M, 1),
  107. #endif
  108. };
  109. int num_tlb_entries = ARRAY_SIZE(tlb_table);