sbc8548.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
  4. *
  5. * Copyright 2007 Embedded Specialties, Inc.
  6. *
  7. * Copyright 2004, 2007 Freescale Semiconductor.
  8. *
  9. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  10. */
  11. #include <common.h>
  12. #include <init.h>
  13. #include <pci.h>
  14. #include <asm/processor.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_pci.h>
  17. #include <fsl_ddr_sdram.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <spd_sdram.h>
  20. #include <netdev.h>
  21. #include <tsec.h>
  22. #include <miiphy.h>
  23. #include <linux/libfdt.h>
  24. #include <fdt_support.h>
  25. void local_bus_init(void);
  26. int board_early_init_f (void)
  27. {
  28. return 0;
  29. }
  30. int checkboard (void)
  31. {
  32. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  33. volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
  34. printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
  35. in_8(rev) >> 4);
  36. /*
  37. * Initialize local bus.
  38. */
  39. local_bus_init ();
  40. out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
  41. out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
  42. return 0;
  43. }
  44. /*
  45. * Initialize Local Bus
  46. */
  47. void
  48. local_bus_init(void)
  49. {
  50. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  51. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  52. uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
  53. sys_info_t sysinfo;
  54. get_sys_info(&sysinfo);
  55. lbc_mhz = sysinfo.freq_localbus / 1000000;
  56. clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
  57. debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
  58. out_be32(&gur->lbiuiplldcr1, 0x00078080);
  59. if (clkdiv == 16) {
  60. out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
  61. } else if (clkdiv == 8) {
  62. out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
  63. } else if (clkdiv == 4) {
  64. out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
  65. }
  66. /*
  67. * Local Bus Clock > 83.3 MHz. According to timing
  68. * specifications set LCRR[EADC] to 2 delay cycles.
  69. */
  70. if (lbc_mhz > 83) {
  71. lcrr &= ~LCRR_EADC;
  72. lcrr |= LCRR_EADC_2;
  73. }
  74. /*
  75. * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
  76. * disable PLL bypass for Local Bus Clock > 83 MHz.
  77. */
  78. if (lbc_mhz >= 66)
  79. lcrr &= (~LCRR_DBYP); /* DLL Enabled */
  80. else
  81. lcrr |= LCRR_DBYP; /* DLL Bypass */
  82. out_be32(&lbc->lcrr, lcrr);
  83. asm("sync;isync;msync");
  84. /*
  85. * According to MPC8548ERMAD Rev.1.3 read back LCRR
  86. * and terminate with isync
  87. */
  88. lcrr = in_be32(&lbc->lcrr);
  89. asm ("isync;");
  90. /* let DLL stabilize */
  91. udelay(500);
  92. out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
  93. out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
  94. }
  95. /*
  96. * Initialize SDRAM memory on the Local Bus.
  97. */
  98. void lbc_sdram_init(void)
  99. {
  100. #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
  101. uint idx;
  102. const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
  103. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  104. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  105. uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
  106. puts(" SDRAM: ");
  107. print_size(size, "\n");
  108. /*
  109. * Setup SDRAM Base and Option Registers
  110. */
  111. set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
  112. set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  113. set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
  114. set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
  115. out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
  116. asm("msync");
  117. out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
  118. out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
  119. asm("msync");
  120. /*
  121. * Issue PRECHARGE ALL command.
  122. */
  123. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
  124. asm("sync;msync");
  125. *sdram_addr = 0xff;
  126. ppcDcbf((unsigned long) sdram_addr);
  127. *sdram_addr2 = 0xff;
  128. ppcDcbf((unsigned long) sdram_addr2);
  129. udelay(100);
  130. /*
  131. * Issue 8 AUTO REFRESH commands.
  132. */
  133. for (idx = 0; idx < 8; idx++) {
  134. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
  135. asm("sync;msync");
  136. *sdram_addr = 0xff;
  137. ppcDcbf((unsigned long) sdram_addr);
  138. *sdram_addr2 = 0xff;
  139. ppcDcbf((unsigned long) sdram_addr2);
  140. udelay(100);
  141. }
  142. /*
  143. * Issue 8 MODE-set command.
  144. */
  145. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
  146. asm("sync;msync");
  147. *sdram_addr = 0xff;
  148. ppcDcbf((unsigned long) sdram_addr);
  149. *sdram_addr2 = 0xff;
  150. ppcDcbf((unsigned long) sdram_addr2);
  151. udelay(100);
  152. /*
  153. * Issue RFEN command.
  154. */
  155. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
  156. asm("sync;msync");
  157. *sdram_addr = 0xff;
  158. ppcDcbf((unsigned long) sdram_addr);
  159. *sdram_addr2 = 0xff;
  160. ppcDcbf((unsigned long) sdram_addr2);
  161. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  162. #endif /* enable SDRAM init */
  163. }
  164. #if defined(CONFIG_SYS_DRAM_TEST)
  165. int
  166. testdram(void)
  167. {
  168. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  169. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  170. uint *p;
  171. printf("Testing DRAM from 0x%08x to 0x%08x\n",
  172. CONFIG_SYS_MEMTEST_START,
  173. CONFIG_SYS_MEMTEST_END);
  174. printf("DRAM test phase 1:\n");
  175. for (p = pstart; p < pend; p++)
  176. *p = 0xaaaaaaaa;
  177. for (p = pstart; p < pend; p++) {
  178. if (*p != 0xaaaaaaaa) {
  179. printf ("DRAM test fails at: %08x\n", (uint) p);
  180. return 1;
  181. }
  182. }
  183. printf("DRAM test phase 2:\n");
  184. for (p = pstart; p < pend; p++)
  185. *p = 0x55555555;
  186. for (p = pstart; p < pend; p++) {
  187. if (*p != 0x55555555) {
  188. printf ("DRAM test fails at: %08x\n", (uint) p);
  189. return 1;
  190. }
  191. }
  192. printf("DRAM test passed.\n");
  193. return 0;
  194. }
  195. #endif
  196. #ifdef CONFIG_PCI1
  197. static struct pci_controller pci1_hose;
  198. #endif /* CONFIG_PCI1 */
  199. #ifdef CONFIG_PCI
  200. void
  201. pci_init_board(void)
  202. {
  203. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  204. int first_free_busno = 0;
  205. #ifdef CONFIG_PCI1
  206. struct fsl_pci_info pci_info;
  207. u32 devdisr = in_be32(&gur->devdisr);
  208. u32 pordevsr = in_be32(&gur->pordevsr);
  209. u32 porpllsr = in_be32(&gur->porpllsr);
  210. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  211. uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
  212. uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  213. uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  214. uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
  215. printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
  216. (pci_32) ? 32 : 64,
  217. (pci_speed == 33000000) ? "33" :
  218. (pci_speed == 66000000) ? "66" : "unknown",
  219. pci_clk_sel ? "sync" : "async",
  220. pci_arb ? "arbiter" : "external-arbiter");
  221. SET_STD_PCI_INFO(pci_info, 1);
  222. set_next_law(pci_info.mem_phys,
  223. law_size_bits(pci_info.mem_size), pci_info.law);
  224. set_next_law(pci_info.io_phys,
  225. law_size_bits(pci_info.io_size), pci_info.law);
  226. first_free_busno = fsl_pci_init_port(&pci_info,
  227. &pci1_hose, first_free_busno);
  228. } else {
  229. printf("PCI: disabled\n");
  230. }
  231. puts("\n");
  232. #else
  233. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  234. #endif
  235. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
  236. fsl_pcie_init_board(first_free_busno);
  237. }
  238. #endif
  239. int board_eth_init(bd_t *bis)
  240. {
  241. tsec_standard_init(bis);
  242. pci_eth_init(bis);
  243. return 0; /* otherwise cpu_eth_init gets run */
  244. }
  245. int last_stage_init(void)
  246. {
  247. return 0;
  248. }
  249. #if defined(CONFIG_OF_BOARD_SETUP)
  250. int ft_board_setup(void *blob, bd_t *bd)
  251. {
  252. ft_cpu_setup(blob, bd);
  253. #ifdef CONFIG_FSL_PCI_INIT
  254. FT_FSL_PCI_SETUP;
  255. #endif
  256. return 0;
  257. }
  258. #endif