ddr.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fsl_ddr_sdram.h>
  8. #include <fsl_ddr_dimm_params.h>
  9. void fsl_ddr_board_options(memctl_options_t *popts,
  10. dimm_params_t *pdimm,
  11. unsigned int ctrl_num)
  12. {
  13. /*
  14. * Factors to consider for clock adjust:
  15. * - number of chips on bus
  16. * - position of slot
  17. * - DDR1 vs. DDR2?
  18. * - ???
  19. *
  20. * This needs to be determined on a board-by-board basis.
  21. * 0110 3/4 cycle late
  22. * 0111 7/8 cycle late
  23. */
  24. popts->clk_adjust = 7;
  25. /*
  26. * Factors to consider for CPO:
  27. * - frequency
  28. * - ddr1 vs. ddr2
  29. */
  30. popts->cpo_override = 10;
  31. /*
  32. * Factors to consider for write data delay:
  33. * - number of DIMMs
  34. *
  35. * 1 = 1/4 clock delay
  36. * 2 = 1/2 clock delay
  37. * 3 = 3/4 clock delay
  38. * 4 = 1 clock delay
  39. * 5 = 5/4 clock delay
  40. * 6 = 3/2 clock delay
  41. */
  42. popts->write_data_delay = 3;
  43. /*
  44. * Factors to consider for half-strength driver enable:
  45. * - number of DIMMs installed
  46. */
  47. popts->half_strength_driver_enable = 0;
  48. }
  49. #ifdef CONFIG_SPD_EEPROM
  50. /*
  51. * Workaround for hardware errata. An i2c address conflict
  52. * existed on earlier boards; the workaround moved the DDR
  53. * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
  54. * if that fails, then fall back to reading at 0x51.
  55. */
  56. void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  57. {
  58. int ret;
  59. #ifdef ALT_SPD_EEPROM_ADDRESS
  60. if (i2c_address == SPD_EEPROM_ADDRESS) {
  61. ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
  62. sizeof(generic_spd_eeprom_t));
  63. if (ret == 0)
  64. return; /* Good data at 0x53 */
  65. memset(spd, 0, sizeof(generic_spd_eeprom_t));
  66. }
  67. #endif
  68. ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
  69. sizeof(generic_spd_eeprom_t));
  70. if (ret) {
  71. printf("DDR: failed to read SPD from addr %u\n", i2c_address);
  72. memset(spd, 0, sizeof(generic_spd_eeprom_t));
  73. }
  74. }
  75. #else
  76. /*
  77. * fixed_sdram init -- doesn't use serial presence detect.
  78. * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
  79. */
  80. phys_size_t fixed_sdram(void)
  81. {
  82. struct ccsr_ddr __iomem *ddr =
  83. (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
  84. out_be32(&ddr->cs0_bnds, 0x0000007f);
  85. out_be32(&ddr->cs1_bnds, 0x008000ff);
  86. out_be32(&ddr->cs2_bnds, 0x00000000);
  87. out_be32(&ddr->cs3_bnds, 0x00000000);
  88. out_be32(&ddr->cs0_config, 0x80010101);
  89. out_be32(&ddr->cs1_config, 0x80010101);
  90. out_be32(&ddr->cs2_config, 0x00000000);
  91. out_be32(&ddr->cs3_config, 0x00000000);
  92. out_be32(&ddr->timing_cfg_3, 0x00000000);
  93. out_be32(&ddr->timing_cfg_0, 0x00220802);
  94. out_be32(&ddr->timing_cfg_1, 0x38377322);
  95. out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
  96. out_be32(&ddr->sdram_cfg, 0x4300C000);
  97. out_be32(&ddr->sdram_cfg_2, 0x24401000);
  98. out_be32(&ddr->sdram_mode, 0x23C00542);
  99. out_be32(&ddr->sdram_mode_2, 0x00000000);
  100. out_be32(&ddr->sdram_interval, 0x05080100);
  101. out_be32(&ddr->sdram_md_cntl, 0x00000000);
  102. out_be32(&ddr->sdram_data_init, 0x00000000);
  103. out_be32(&ddr->sdram_clk_cntl, 0x03800000);
  104. asm("sync;isync;msync");
  105. udelay(500);
  106. #ifdef CONFIG_DDR_ECC
  107. /* Enable ECC checking */
  108. out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
  109. #else
  110. out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
  111. #endif
  112. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  113. }
  114. #endif