sbc8349.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sbc8349.c -- WindRiver SBC8349 board support.
  4. * Copyright (c) 2006-2007 Wind River Systems, Inc.
  5. *
  6. * Paul Gortmaker <paul.gortmaker@windriver.com>
  7. * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
  8. */
  9. #include <common.h>
  10. #include <ioports.h>
  11. #include <mpc83xx.h>
  12. #include <asm/mpc8349_pci.h>
  13. #include <i2c.h>
  14. #include <spd_sdram.h>
  15. #include <miiphy.h>
  16. #if defined(CONFIG_OF_LIBFDT)
  17. #include <linux/libfdt.h>
  18. #endif
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int fixed_sdram(void);
  21. void sdram_init(void);
  22. #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
  23. void ddr_enable_ecc(unsigned int dram_size);
  24. #endif
  25. #ifdef CONFIG_BOARD_EARLY_INIT_F
  26. int board_early_init_f (void)
  27. {
  28. return 0;
  29. }
  30. #endif
  31. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  32. int dram_init(void)
  33. {
  34. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  35. u32 msize = 0;
  36. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  37. return -1;
  38. /* DDR SDRAM - Main SODIMM */
  39. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  40. #if defined(CONFIG_SPD_EEPROM)
  41. msize = spd_sdram();
  42. #else
  43. msize = fixed_sdram();
  44. #endif
  45. /*
  46. * Initialize SDRAM if it is on local bus.
  47. */
  48. sdram_init();
  49. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  50. /*
  51. * Initialize and enable DDR ECC.
  52. */
  53. ddr_enable_ecc(msize * 1024 * 1024);
  54. #endif
  55. /* set total bus SDRAM size(bytes) -- DDR */
  56. gd->ram_size = msize * 1024 * 1024;
  57. return 0;
  58. }
  59. #if !defined(CONFIG_SPD_EEPROM)
  60. /*************************************************************************
  61. * fixed sdram init -- doesn't use serial presence detect.
  62. ************************************************************************/
  63. int fixed_sdram(void)
  64. {
  65. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  66. u32 msize = CONFIG_SYS_DDR_SIZE;
  67. u32 ddr_size = msize << 20; /* DDR size in bytes */
  68. u32 ddr_size_log2 = __ilog2(msize);
  69. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  70. im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  71. #if (CONFIG_SYS_DDR_SIZE != 256)
  72. #warning Currently any ddr size other than 256 is not supported
  73. #endif
  74. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  75. #warning Chip select bounds is only configurable in 16MB increments
  76. #endif
  77. im->ddr.csbnds[2].csbnds =
  78. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  79. (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  80. CSBNDS_EA_SHIFT) & CSBNDS_EA);
  81. im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
  82. /* currently we use only one CS, so disable the other banks */
  83. im->ddr.cs_config[0] = 0;
  84. im->ddr.cs_config[1] = 0;
  85. im->ddr.cs_config[3] = 0;
  86. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  87. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  88. im->ddr.sdram_cfg =
  89. SDRAM_CFG_SREN
  90. #if defined(CONFIG_DDR_2T_TIMING)
  91. | SDRAM_CFG_2T_EN
  92. #endif
  93. | SDRAM_CFG_SDRAM_TYPE_DDR1;
  94. #if defined (CONFIG_DDR_32BIT)
  95. /* for 32-bit mode burst length is 8 */
  96. im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
  97. #endif
  98. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  99. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  100. udelay(200);
  101. /* enable DDR controller */
  102. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  103. return msize;
  104. }
  105. #endif/*!CONFIG_SYS_SPD_EEPROM*/
  106. int checkboard (void)
  107. {
  108. puts("Board: Wind River SBC834x\n");
  109. return 0;
  110. }
  111. /*
  112. * if board is fitted with SDRAM
  113. */
  114. #if defined(CONFIG_SYS_BR2_PRELIM) \
  115. && defined(CONFIG_SYS_OR2_PRELIM) \
  116. && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
  117. && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
  118. /*
  119. * Initialize SDRAM memory on the Local Bus.
  120. */
  121. void sdram_init(void)
  122. {
  123. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  124. volatile fsl_lbc_t *lbc = &immap->im_lbc;
  125. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  126. const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
  127. LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
  128. LSDMR_WRC3 | LSDMR_CL3;
  129. puts("\n SDRAM on Local Bus: ");
  130. print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  131. /*
  132. * Setup SDRAM Base and Option Registers, already done in cpu_init.c
  133. */
  134. /* setup mtrpt, lsrt and lbcr for LB bus */
  135. lbc->lbcr = 0x00000000;
  136. /* LB refresh timer prescal, 266MHz/32 */
  137. lbc->mrtpr = 0x20000000;
  138. /* LB sdram refresh timer, about 6us */
  139. lbc->lsrt = 0x32000000;
  140. asm("sync");
  141. /*
  142. * Configure the SDRAM controller Machine Mode Register.
  143. */
  144. /* 0x40636733; normal operation */
  145. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  146. /* 0x68636733; precharge all the banks */
  147. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  148. asm("sync");
  149. *sdram_addr = 0xff;
  150. udelay(100);
  151. /* 0x48636733; auto refresh */
  152. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  153. asm("sync");
  154. /*1 times*/
  155. *sdram_addr = 0xff;
  156. udelay(100);
  157. /*2 times*/
  158. *sdram_addr = 0xff;
  159. udelay(100);
  160. /*3 times*/
  161. *sdram_addr = 0xff;
  162. udelay(100);
  163. /*4 times*/
  164. *sdram_addr = 0xff;
  165. udelay(100);
  166. /*5 times*/
  167. *sdram_addr = 0xff;
  168. udelay(100);
  169. /*6 times*/
  170. *sdram_addr = 0xff;
  171. udelay(100);
  172. /*7 times*/
  173. *sdram_addr = 0xff;
  174. udelay(100);
  175. /*8 times*/
  176. *sdram_addr = 0xff;
  177. udelay(100);
  178. /* 0x58636733; mode register write operation */
  179. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  180. asm("sync");
  181. *sdram_addr = 0xff;
  182. udelay(100);
  183. /* 0x40636733; normal operation */
  184. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  185. asm("sync");
  186. *sdram_addr = 0xff;
  187. udelay(100);
  188. }
  189. #else
  190. void sdram_init(void)
  191. {
  192. puts(" SDRAM on Local Bus: Disabled in config\n");
  193. }
  194. #endif
  195. #if defined(CONFIG_OF_BOARD_SETUP)
  196. int ft_board_setup(void *blob, bd_t *bd)
  197. {
  198. ft_cpu_setup(blob, bd);
  199. #ifdef CONFIG_PCI
  200. ft_pci_setup(blob, bd);
  201. #endif
  202. return 0;
  203. }
  204. #endif