onenand.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008-2009 Samsung Electronics
  4. * Kyungmin Park <kyungmin.park@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <linux/compat.h>
  8. #include <linux/mtd/mtd.h>
  9. #include <linux/mtd/onenand.h>
  10. #include <linux/mtd/samsung_onenand.h>
  11. #include <onenand_uboot.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. int onenand_board_init(struct mtd_info *mtd)
  15. {
  16. struct onenand_chip *this = mtd->priv;
  17. struct s5pc100_clock *clk =
  18. (struct s5pc100_clock *)samsung_get_base_clock();
  19. struct samsung_onenand *onenand;
  20. int value;
  21. this->base = (void *)S5PC100_ONENAND_BASE;
  22. onenand = (struct samsung_onenand *)this->base;
  23. /* D0 Domain memory clock gating */
  24. value = readl(&clk->gate_d01);
  25. value &= ~(1 << 2); /* CLK_ONENANDC */
  26. value |= (1 << 2);
  27. writel(value, &clk->gate_d01);
  28. value = readl(&clk->src0);
  29. value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
  30. value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
  31. writel(value, &clk->src0);
  32. value = readl(&clk->div1);
  33. value &= ~(3 << 16); /* PCLKD1_RATIO */
  34. value |= (1 << 16);
  35. writel(value, &clk->div1);
  36. writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
  37. while (!(readl(&onenand->int_err_stat) & RST_CMP))
  38. continue;
  39. writel(RST_CMP, &onenand->int_err_ack);
  40. /*
  41. * Access_Clock [2:0]
  42. * 166 MHz, 134 Mhz : 3
  43. * 100 Mhz, 60 Mhz : 2
  44. */
  45. writel(0x3, &onenand->acc_clock);
  46. writel(INT_ERR_ALL, &onenand->int_err_mask);
  47. writel(1 << 0, &onenand->int_pin_en); /* Enable */
  48. value = readl(&onenand->int_err_mask);
  49. value &= ~RDY_ACT;
  50. writel(value, &onenand->int_err_mask);
  51. s3c_onenand_init(mtd);
  52. return 0;
  53. }