lowlevel_init.S 3.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2009 Samsung Electronics
  4. * Kyungmin Park <kyungmin.park@samsung.com>
  5. * Minkyu Kang <mk7.kang@samsung.com>
  6. */
  7. #include <config.h>
  8. #include <asm/arch/cpu.h>
  9. #include <asm/arch/power.h>
  10. /*
  11. * Register usages:
  12. *
  13. * r5 has zero always
  14. */
  15. .globl lowlevel_init
  16. lowlevel_init:
  17. mov r9, lr
  18. /* r5 has always zero */
  19. mov r5, #0
  20. ldr r8, =S5PC100_GPIO_BASE
  21. /* Disable Watchdog */
  22. ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
  23. orr r0, r0, #0x0
  24. str r5, [r0]
  25. /* setting SRAM */
  26. ldr r0, =S5PC100_SROMC_BASE
  27. ldr r1, =0x9
  28. str r1, [r0]
  29. /* S5PC100 has 3 groups of interrupt sources */
  30. ldr r0, =S5PC100_VIC0_BASE @0xE4000000
  31. ldr r1, =S5PC100_VIC1_BASE @0xE4000000
  32. ldr r2, =S5PC100_VIC2_BASE @0xE4000000
  33. /* Disable all interrupts (VIC0, VIC1 and VIC2) */
  34. mvn r3, #0x0
  35. str r3, [r0, #0x14] @INTENCLEAR
  36. str r3, [r1, #0x14] @INTENCLEAR
  37. str r3, [r2, #0x14] @INTENCLEAR
  38. /* Set all interrupts as IRQ */
  39. str r5, [r0, #0xc] @INTSELECT
  40. str r5, [r1, #0xc] @INTSELECT
  41. str r5, [r2, #0xc] @INTSELECT
  42. /* Pending Interrupt Clear */
  43. str r5, [r0, #0xf00] @INTADDRESS
  44. str r5, [r1, #0xf00] @INTADDRESS
  45. str r5, [r2, #0xf00] @INTADDRESS
  46. /* for UART */
  47. bl uart_asm_init
  48. /* for TZPC */
  49. bl tzpc_asm_init
  50. 1:
  51. mov lr, r9
  52. mov pc, lr
  53. /*
  54. * system_clock_init: Initialize core clock and bus clock.
  55. * void system_clock_init(void)
  56. */
  57. system_clock_init:
  58. ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
  59. /* Set Clock divider */
  60. ldr r1, =0x00011110
  61. str r1, [r8, #0x304]
  62. ldr r1, =0x1
  63. str r1, [r8, #0x308]
  64. ldr r1, =0x00011301
  65. str r1, [r8, #0x300]
  66. /* Set Lock Time */
  67. ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
  68. str r1, [r8, #0x000] @ APLL_LOCK
  69. str r1, [r8, #0x004] @ MPLL_LOCK
  70. str r1, [r8, #0x008] @ EPLL_LOCK
  71. str r1, [r8, #0x00C] @ HPLL_LOCK
  72. /* APLL_CON */
  73. ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
  74. str r1, [r8, #0x100]
  75. /* MPLL_CON */
  76. ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
  77. str r1, [r8, #0x104]
  78. /* EPLL_CON */
  79. ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
  80. str r1, [r8, #0x108]
  81. /* HPLL_CON */
  82. ldr r1, =0x80600603
  83. str r1, [r8, #0x10C]
  84. /* Set Source Clock */
  85. ldr r1, =0x1111 @ A, M, E, HPLL Muxing
  86. str r1, [r8, #0x200] @ CLK_SRC0
  87. ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
  88. str r1, [r8, #0x204] @ CLK_SRC1
  89. ldr r1, =0x9000 @ ARMCLK/4
  90. str r1, [r8, #0x400] @ CLK_OUT
  91. /* wait at least 200us to stablize all clock */
  92. mov r2, #0x10000
  93. 1: subs r2, r2, #1
  94. bne 1b
  95. mov pc, lr
  96. /*
  97. * uart_asm_init: Initialize UART's pins
  98. */
  99. uart_asm_init:
  100. mov r0, r8
  101. ldr r1, =0x22222222
  102. str r1, [r0, #0x0] @ GPA0_CON
  103. ldr r1, =0x00022222
  104. str r1, [r0, #0x20] @ GPA1_CON
  105. mov pc, lr
  106. /*
  107. * tzpc_asm_init: Initialize TZPC
  108. */
  109. tzpc_asm_init:
  110. ldr r0, =0xE3800000
  111. mov r1, #0x0
  112. str r1, [r0]
  113. mov r1, #0xff
  114. str r1, [r0, #0x804]
  115. str r1, [r0, #0x810]
  116. ldr r0, =0xE2800000
  117. str r1, [r0, #0x804]
  118. str r1, [r0, #0x810]
  119. str r1, [r0, #0x81C]
  120. ldr r0, =0xE2900000
  121. str r1, [r0, #0x804]
  122. str r1, [r0, #0x810]
  123. mov pc, lr